Asa Manual 2006

8/12/2019 Asa Manual 2006

http://slidepdf.com/reader/full/asa-manual-2006 1/90

Limited InternalDESCRIPTION 1 ( 90 )

/ EAB/UZ/DM SES 13/1551-ANZ 211 60 Uen

/ EAB/UZ/DM (S-E Sund) 2006-08-18 C

Prepared (also subject responsible if other) No

Approved Checked Date Rev Reference

ASA210C, General Assembler Instructions

Contents Page

1 General . .. . .. . .. . .. .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. . .. . . 51.1 Revision Information . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 51.2 Abstract . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 5

1.3 Implementation . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 51.4 The Assembler Language . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 51.5 Machine Characteristics . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 61.6 Forlopp Support . . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 6

2 Instructions for Reading from Store . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . 62.1 RS, Read from Store . . . .. . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 62.2 RSE, Read from Store Extended . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 72.3 RSI, Read from Store Indexed . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . 82.4 RSII, Read from Store Indexed Indirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.5 RSS, Read Subvariable from Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.6 RDP, Read Dynamic Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.7 RDB, Read from Dynamic Buffer . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 112.8 RDBI, Read from Dynamic Buffer Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112.9 RCB, Read from Communication Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.10 RCP, Read Communication Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132.11 RFID, Read Forlopp Identity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3 Instructions for writing in Store . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . 143.1 WS, Write in Store . . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 143.2 WSE, Write in Store Extended . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 153.3 WSI, Write in Store Indexed . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. 153.4 WSII, Write in Store Indexed Indirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.5 WSS, Write Subvariable in Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183.6 WHC, Write Halfword Constant . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 183.7 WZ, Write Zeros . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 193.8 WO, Write Ones . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 19

3.9 FIRSI, File Insert Register to Store Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.10 WDB, Write in Dynamic Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.11 WDBI, Write in Dynamic Buffer Indexed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.12 WCB, Write in Communication Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.13 CCBI, Copy Communication Buffer Indexed .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243.14 WFID, Write Forlopp Identity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4 Register Instructions . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 254.1 LCC, Load Character Constant . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 254.2 LHC, Load Halfword Constant . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . 264.3 LWCD, Load Word Constant Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264.4 LHCE, Load Halfword Constant Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.5 LAT, Load Absolute Time . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 274.6 MFR, Move from Register . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . . . . . . . . . . .. . . 28

A4 XSEIF R3

8/12/2019 Asa Manual 2006







4.7 MFRE, Move from Register Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294.8 MTR, Move To Register . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 294.9 TNB , Translate Number to Bit vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.10 CFID, Clear Forlopp Identity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304.11 TFID, Test Forlopp Identity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5 Arithmetic Instructions . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 315.1 AR, Add Register to Register . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 315.2 ARD, Add Register to Register Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325.3 ACC, Add Character Constant To Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325.4 AWC, Add Word Constant to register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.5 AWCD, Add Word Constant To Register Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.6 AHCS, Add Halfword Constant To Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335.7 SR, Subtract Register from Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345.8 SRD, Subtract Register from Register Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355.9 SCC, Subtract Character Constant from Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355.10 SWC, Subtract Word Constant from Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365.11 SWCD, Subtract Word Constant from Register Double .... .. ... ... ... ... ... .. 365.12 SHCS, Subtract Halfword Constant from Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375.13 MR, Multiply Register . . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . 375.14 DR, Divide Register . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 38

6 Shift and Logical Instructions . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . . .. . . . . . . . . 386.1 SHL, SHift Left . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 386.2 SHLD, SHift Left Double . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 396.3 SHR, SHift Right .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 396.4 SHRD, SHift Right Double . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 406.5 ROL, ROtate Left . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 406.6 ROLD, ROtate Left Double . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 416.7 ROR, ROtate Right . . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 416.8 RORD, ROtate Right Double . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. 426.9 ER, Exclusive or in Register . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 426.10 OR, Logical Or in Register . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 436.11 NR, Logical and in Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446.12 NWC, Logical and with Word Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

7 Local Jump Instructions . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 457.1 JLN, Jump Local Normal . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 457.2 JLL, Jump Local and Link . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 46

7.3 JOR, Jump on One in Result Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467.4 JZR, Jump on Zero in Result Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467.5 JEC, Jump on Equality with Character Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.6 JUC, Jump on Unequality with Character Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.7 JER, Jump on Equality between Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.8 JUR, Jump on Unequality between Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487.9 JGT, Jump on Greater Than . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 487.10 JLT, Jump on Less Than . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 497.11 JTR, Jump on Table Indexed by Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497.12 JTS, Jump on Table Indexed by Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

8 Signal Transmission Instructions . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 518.1 SSN, Send Signal Normal . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 51

8/12/2019 Asa Manual 2006







8.2 SSIN, Send Signal Indirect Normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518.3 SSPD, Send Signal from Process Register Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528.4 SSL, Send Signal and Link . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . . .. . . 538.5 SSIL, Send Signal Indirect and Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538.6 SSPL, Send Signal from Process register Linked .. . . . . . . . . . . . . . . . . . . . . . . . . . . . 548.7 SSB, Send Signal via Job Buffer . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 558.8 SSBD, Send Signal via Job Buffer Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558.9 SSIB, Send Signal Indirect via Job Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568.10 SSIBD Send Signal Indirect via Job Buffer Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568.11 SCBS, Send Combined Backward Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.12 RCBS, Retrieve Combined Backward Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.13 SSPB, Send Signal from Process Register via Job Buffer .. ... ... ... ... ... .. 588.14 SSPBD Send Signal from Process Registers via Job Buffer Double .. .. .. .. 598.15 XSTQ, Send Signal via Time Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608.16 XSTQD Send Signal via Time Queue Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628.17 SSRP, Send Signal to RP . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . 648.18 SSRPE Send Signal TO RP Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658.19 SSIP, Send Signal to IPNA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668.20 SSIPD, Send Signal to IPNA Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688.21 XRST, Read from Signal Sending Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698.22 RBD, Receive Bulk Data . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . 708.23 SSRPB, Send Bulk Signal to RP . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 71

9 Miscellaneous Instructions . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. 739.1 EP, End of Program . . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 739.2 SRT , Set Return Time . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 74

10 Search Instructions . . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . 7410.1 BLO, Bit search for Leftmost One in Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7410.2 BLOD, Bit search for Leftmost One in Register Double .. ... ... ... .. ... ... ... . 7510.3 CS, Compare String . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 7510.4 FESR, File search for Equality between Store and Register ... ... ... ... ... .. 7610.5 FCZS, File search for Change to Zero in Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

11 Macro Instructions . . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . .. 7811.1 ADDR, Load Dened Address .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . 7811.2 BLNR, Load Block Reference Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7911.3 DUPL, Duplicate Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7911.4 ERD, Exclusive or in Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

11.5 JECD, Jump on Eq with Char Constant Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8011.6 JERD, Jump on Equality between Register Double . . . . . . . . . . . . . . . . . . . . . . . . . . . 8111.7 JGETD Jump on Greater Than or Equal Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8111.8 JGTD, Jump on Greater Than Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8211.9 JLETD Jump on Less Than or Equal Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8211.10 JLTD, Jump on Less Than Double . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8211.11 JUCD, Jump on Unequality with Char Const Double .. .. ... .. ... ... ... ... ... .. 8311.12 JURD, Jump on Unequality between Register Double . ... ... ... ... ... ... ... .. 8311.13 LBNBA Load Base Address Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8411.14 LBNSL, Load Signal Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8411.15 LCCE, Load Character Constant Extended .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8411.16 LWC, Load Word Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8511.17 NHC, Logical aNd with Halfword Constant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

8/12/2019 Asa Manual 2006







11.18 RECEIVE, Receive a Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8611.19 SGLOC Signal Group Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8611.20 SSLL, Send Signal Local and Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8711.21 SSLN, Send Signal Local Normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8711.22 TQINF Time Queue Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8811.23 TQINFI Time Queue Information Indirect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8911.24 VAL , Load Dened Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8911.25 XLLR, Load Location in Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

8/12/2019 Asa Manual 2006







1 General

1.1 Revision Information

This Descripttion is based on 13/1551-ANZ 211 60 Rev B.

Changes in this document are

a Clarication that the registers r4 and r5 are only used and set by the PLEXcompiler for the instructions RSII and WSII. When writing the instructionmanually nothing should be dened for the registers r4 and r5, only theregisters r1, r2 and r3 should be dened.

b —

1.2 Abstract

This paper denes and describes assembler instructions in ASA210C. It isvalid for APZ 212 20 and later APZs.

The paper describes instructions which are of a general nature only. Instructionswhich are used by the operating system for special purposes are described inthe document ’ASA210C, Operating System Assembler Instructions’.

Parameters in the instructions are dened in the document ’ASA210C,Assembler Instruction Parameters’.

Binary formats of the machine operations are described in the document’Machine Operation Binary Formats’.

1.3 Implementation

This document is valid for APZ 212 20 and later APZs. When nothing elseis said in the sections ’implementation’ below it implies that the machineinstruction is implemented for all APZ models.

1.4 The Assembler Language

The assembler language ASA210C is built up of a number of assemblerinstructions. Assembler instructions are separated by semicolons.

Each assembler instruction has its counterpart in one or several machineoperations. For instance, the assembler instruction RS, Read from Store,can be compiled to one of the three machine instructions RSA, RSU or RSLdepending on length of the a-parameter. The assembler instruction is to beused in source code and when assembler corrections are written.

All numbers are treated as positive integers.

8/12/2019 Asa Manual 2006







A program label is dened by writing the name followed by a right-handparenthesis before the keyword to which the reference is to be made in theassembler instruction.

The assembler instructions may have parameters which are separated byfollowing characters:

a ,

A comma normally separates the parameters.

b -

A dash between two parameters indicates that data is transferred betweenthe parameters. The transfer is always done from the right-hand to theleft-hand parameter.

c /

A slash separates variables and subvariables or a process register andpart of that register.

1.5 Machine Characteristics

APZ 212 is a 32-bit machine. Assembler instructions which work differentlyon different register lengths have names which end on letter D. That is, theassembler instruction AR, Add Register, will inuence the 16 lower bits in aregister whereas the assembler instruction ARD will affect all the 32 bits in adouble word.

1.6 Forlopp Support

In order to support the ’forlopp’ concept, all buffered signal sending instructionsdescribed below also transfer the forlopp identity of the current forlopp assignal data.

The current forlopp identity is cleared at the end of a job before a new signal istaken out from the signal buffer. Then, when a new signal is entered, the forloppidentity from that signal is loaded as current forlopp identity.

2 Instructions for Reading from Store

2.1 RS, Read from Store

a Format:

RS r-var;

b Function:

8/12/2019 Asa Manual 2006







Variable var is fetched from the store and stored right-justied in processregister r. Variables larger than 32 bits and subvariables can not be read.

c Example:

RS WR1-CLINK;

The contents of variable CLINK is transferred to register WR1.

d Implementation:

The assembler instruction RS generates one of the machine operationsRSA, RSU or RSL.RSA will be generated if the base address of thevariable is 1-63, RSU if it is 64-255 and RSL if it is 256-4095.

2.2 RSE, Read from Store Extended

a Format:

RSE r-var;

b Function:

Variable var, which has a length of 2, 4 or 8 16-bit words, is fetched fromthe store and stored in process register r, r+1, r+2 etc. The rst word in thevariable is stored in process register r, the next word in r+1 and so on.

The variable may not be a subvariable.

c Example:

RSE WR6-MESSAGE;

Assume that variable MESSAGE with a length of 64 bits is to be storedfrom and including register WR6.

The rst word in MESSAGE is stored in WR6, the second word is stored inWR7, the third word is stored in WR8 and the fourth word is stored in WR9.

d Note:

Parameter r must not be a temporary variable.

e Implementation:

The assembler instruction RSE generates one of the machine operationsRSEU or RSEL.RSEU will be generated if the base address of var is1-255, else RSEL will be generated.

8/12/2019 Asa Manual 2006







2.3 RSI, Read from Store Indexed

a Format:

RSI r1-var, r2, m;

b Function:

The instruction moves all or part of a variable array from the store toconsecutive process registers. (The pointer has a xed value or is notused, the index runs consecutively.)

Variables larger than 32 bits and subvariables can not be read.

- IR species the index to the rst variable which is to be read.

IR is not changed.

- r1 species the register for the rst variable.

- r2 species a register, which contains the number of variables to betransferred.

If the contents of register r2=0 no transfer is carried out.

The contents of r2 are always unaffected.

- m species the maximum value for the contents of register r2.

If the contents are greater than m+1, program error actions will be taken. 0<= m <= 63.

c Example:

RSI DR0-DUMPVAR, PR0, 7; (IR=2, PR0=5)

The ve variables with index = 2, 3, 4, 5 and 6 in variable array DUMPVARare transferred to register DR0, DR1, DR2, DR3 and DR4.

d Note 1:

APS checks that r1’s address + m <= 63 to prevent wrap-around.

e Note 2:

Parameter r1 must not be a temporary variable.

f Implementation:

The assembler instruction RSI generates one of the machine operationsRSIU or RSIL. RSIU will be generated if the base address of var is 1-255,else RSIL will be generated.

8/12/2019 Asa Manual 2006







2.4 RSII, Read from Store Indexed Indirect

a Format:

RSII r1-r2, r3, r4, r5;

b Function:

The instruction moves all or part of a variable array from the store toconsecutive processor registers. The variable and the register where therst index is to be loaded is addressed indirectly.The pointer has a xedvalue or is not used, the index runs consecutively from a given start value.

Variables larger than 32 bits and subvariables can not be read.

- Processor register r1 species which register that is to be loaded withthe rst variable, see Note 2 below.

- r2 is the base address number of the variable to read.

- r3 is the number of indices to be read. If r3 = 0 then the entire variablewill be read.

- r4 is the rst used data register in register memory, RM, DR0 - DR23.

- r5 is the last used data register in register memory, RM, DR0 - DR23.

- IR contains the rst index of the variable to be read.

- PR0 contains a valid pointer (if used).

The parameters r4 and r5 are only used by the register allocation algorithmswithin APS. They do not affect the binary format of the instruction, andhence should not be dened when writng this instruction manually.

c Example:

RSII DR0-WR0,WR1; (WR1=3, IR=2, PR0=5)

Three indexes from a variable is read to the processor registers. The baseaddress number of the variable is taken from WR0.

d Note 1:

It is only possible to read data to data registers (DR0-DR23).

e Note 2:

The address of the register to be given in register r1 is expressed as thenormal register address dened in the document ’ASA201C, assemblerinstruction parameters’. DR0 has the address 6, DR1 has the address 7and so on. DR23 has the address 29.

8/12/2019 Asa Manual 2006







2.5 RSS, Read Subvariable from Store

a Format:

RSS r-var/vln;

b Function:

A subvariable which is included in the composite variable var is fetchedfrom the store and stored right-justied in process register r. Variable varmay not be a subvariable. The subvariable is pointed out with its size in vl

and its sequence number in n. The subvariable may be max 32 bits.c Example:

RSS WR12-CLINK/H3;

The subvariable which corresponds to half-word 3 within the compositevariable CLINK is transferred to process register WR12.

d Implementation:

The assembler instruction RSS generates one of the machine operationsRSSU or RSSL. RSSU will be generated if the base address of var is1-255, else RSSL will be generated.

2.6 RDP, Read Dynamic Buffer Pointer

a Format:

RDP r-var;

b Function:

Buffer variable var is fetched from the store and stored right-justied inprocess register r b15-b0. Process register r is cleared before the transfer.The trace bit for writing in a variable in the base address table is saved inbit 31 in register r together with the length of the variable, which is storedin bits 16-27. Variable var shall have a length of 16 bits and may not beindexed.

c Example :

RDP WR0-BUFVAR;

Buffer variable BUFVAR is transferred to register WR0 b15-b0. The baseaddress table’s bit for writing in a variable and a base address are storedin register r b31-b16.

8/12/2019 Asa Manual 2006







2.7 RDB, Read from Dynamic Buffer

a Format:

RDB r-vlb, vl;

b Function:

Transfer of data to process register r from a (sub)-variable in a dynamicbuffer.

Pointer register PR1 contains a pointer to the buffer. Index register IRcontains the index for the relevant variable in the buffer. Parameter vlspecies the length of the variable. Parameter vlb is used for specifying asubvariable within the indicated variable.

c Example:

RDB WR3-H0,H; The 8-bit variable which is pointed out by a bufferpointer in process register PR1 and an index in register IR is transferredright-justied to process register WR3, which is cleared before the transfer.

d Note:

THIS INSTRUCTION MAY NOT BE USED IN ASA SECTORS INPROGRAMS.

e Additional information:

Addressing takes place in the following way:

The bank’s absolute address WA is read from the base address whosenumber is known to the microprogram. The contents of (PR1[bit 0-11])*2exp(V+Q) are added to WA. This gives the address to the rst word ofthe buffer. Parameter vl and the contents of register IR are then usedto calculate the address within the buffer to the word which containsthe relevant variable. This address is added to (WA+(PR1[bit 0-11])*2exp(V+Q)). Reading can then take place from the data store and the

specied subvariable is retrieved.V = 2log (variable length)

Q = 2log (number of variables in array of variables)

2.8 RDBI, Read from Dynamic Buffer Indexed

a Format:

RDBI r1/vlm-vlb, vl, r2, m;

b Function:

8/12/2019 Asa Manual 2006







Transport of data to consecutive process registers from a (sub)variablearray in a dynamic buffer.If the subvariable and the register variable areless than 16 bit the data are stored packed according to ’vlm’.

r1 indicates register for the rst variable.

vlm species the length and rst position for the register variable whenstored in r1.

vlb species subvariable within the variable.

vl species the length of the variable.

r2 species the number of variables that shall be transferred.

If r2=0, the instruction does not execute any action.

m species the maximum value for the contents of register r2.

If the contents are greater than m+1, software error actions are taken. 0<= m <= 63.

Process register PR1 (bit 0-11) contains pointer to the buffer.

Index register IR contains index to the rst buffer variable.

If the origin (sub)variable is greater than the register variable the data willbe truncated.

If the origin (sub)variable is smaller than the register variable the registervariable will be lled with zeros from most signicant bit.

Parts of bits 0-15 of process registers which are not written with registervariables remain unchanged.

c d=Example:

RDBI DR0/H0-H0, H, AR2, 25; (IR=0,AR2=10)

From the buffer pointed to by PR1, with the length 8 bits, 10 variables areread to process registers, the rst variable will be stored in DR0/H0, thesecond variable in DR0/H1, the third in DR1/H0 an so forth.

d Note:


e Note 1:


8/12/2019 Asa Manual 2006







f Note 2:


2.9 RCB, Read from Communication Buffer

a Format:

RCB r-var/vlb;

b Function:

Transfer of data to process register r from a (sub) variable in aCommunication Buffer. Parameter var is the base address of the memorybank where the Communication Buffer is allocated.

Pointer register PR0 contains a pointer to the buffer. Index register IRcontains the index for the relevant variable in the buffer.

The Communication Buffer variable size is dened by Base Address Tablefor memory bank. Default variable size is 16 bits. Larger variables than 16bits can not be used.

Parameter vlb is used for specifying a subvariable within the indicated

variable.

c Note:


2.10 RCP, Read Communication Buffer Pointer

a Format:

RCP r-var,h;

b Function:

Buffer variable var corresponding to a Communication Buffer is fetchedfrom store.

Bits 0-23 of the buffer variable contain the individual pointer to theCommunication Buffer. Bits 24-31 of the buffer variable contain the baseaddress of the memory bank. If bits 24-31 of variable var are equal toprogram constant h, the bits 24-31 are cleared to zero before the variableis stored right-justied in register r.

If bits 24-31 are not equal to program constant h, software error actionsare taken.

8/12/2019 Asa Manual 2006







Variable var shall have a length of 32 bits and may not be indexed. Thevariable may be allocated in a le (addressed by pointer).

If the trace bit T for writing in a variable from the base address table is set itis saved in B23 in register r, and B30 in PR1 is set to one.

c Note:


2.11 RFID, Read Forlopp Identitya Format:

RFID var;

b Function:

The forlopp identity (FID) is copied from variable var to the registerEXECFID. Variable var shall have a length of 32 bits. The variable mustnot be a subvariable.RFID is intended to be used directly after receptionof signals which do not have a FID in the signal header. Such signals arereceived with the ENTER statement (EXTERN).If the FID is zero, softwarerecovery actions will be taken.

c Example:

RFID COMMANDFID;

The forlopp identity is transferred from the variable COMMANDFID to theregister EXECFID.

3 Instructions for writing in Store

3.1 WS, Write in Store

a Format:

WS var-r;

b Function:

The contents of the process register r are stored right-justied in variablevar in the store. If the variable is smaller than 32 bits, that part of r whichis not contained in the variable is truncated from the left. That part of thevariable (if any) which is larger than 16/32 bits is not affected. Subvariablescannot be written.

c Example:

8/12/2019 Asa Manual 2006







WS CLINK-WR1;

Process register WR1 is stored in variable CLINK.

d Implementation:

The assembler instruction WS generates one of the machine operationsWSA, WSU or WSL. WSA will be generated if the base address of thevariable is 1-63, WSU if it is 64-255 and WSL if it is 256-4095.

3.2 WSE, Write in Store Extended

a Format:

WSE var-r;

b Function:

Transfer of contents of process register r, r+1 etc. to a variable in the datastore. The variable, which must have a size of 2, 4 or 8 words, receivesthe contents of process register r in the rst word, the contents of processregister r+1 in the second word and so on. If the size of the variable is 1word, WSE will do nothing. The variable may not be a subvariable.

c Example:

WSE MESSAGE-WR8;

Assume that variable MESSAGE with a length of 64 bits is to receive thevalue of process register WR8, WR9, WR10 and WR11.

Transfer of WR8 to word 0 in MESSAGE, of WR9 to word 1 in MESSAGE,of WR10 to word 2 in MESSAGE and of WR11 to word 3 in MESSAGE.

d Note:


e Implementation:

The assembler instruction WSE generates one of the machine operationsWSEU or WSEL. WSEU will be generated if the base address of var is1-255, else WSEL will be generated.

3.3 WSI, Write in Store Indexed

a Format:

WSI var-r1, r2, m;

b Function:

8/12/2019 Asa Manual 2006







This instruction transfers the contents of consecutive process registers tovariables in a variable array in the store. (The pointer has a xed value ordoes not occur, the index runs consecutively). The contents of the processregisters are placed right-justied in the variables. If the variables are lessthan 32 bits, that part of the process registers which cannot be containedin the variables is truncated from the left. In the case of variables largerthan 16/32 bits, bit 16/32 and upwards are not affected. Subvariablescannot be written.

- IR species an index to the rst receiving variable.

- r1 species the rst register which is to be transferred.

- r2 species a register, which contains the number of registers to betransferred. If the contents of register r2=0 no transfer is carried out. Thecontents of r2 are always unaffected.

- m species the maximum value for the contents of register r2. If thecontents are greater than m+1, program error actions are taken. 0 <=m <= 63.

c Example:

WSI DUMPVAR - WR22, PR0, 7; (IR=2, PR0=5)

Bits 0-7 of process registers WR22, WR23, WR24, WR25 and WR26 areentered in the ve variables with indexes 2, 3, 4, 5 and 6 in variable arrayDUMPVAR (the variables have a length of 8 bits).

d Note 1:


e Note 2:


f Note 3:

APS does not accept variables larger than 32 bit

g Implementation:

The assembler instruction WSI generates one of the machine operationsWSIU or WSIL. WSIU will be generated if the base address of var is 1-255,else WSIL will be generated.

3.4 WSII, Write in Store Indexed Indirect

a Format:

WSII r1-r2, r3, r4, r5;

8/12/2019 Asa Manual 2006







b Function:

This instruction transfers the contents of consecutive process registers tovariables in a variable array in the store. Both the variable and the rstregister where data is fetched from is addressed indirectly. The pointer hasa xed value or is not used, the index runs consecutively from the givenstart value.

Variables larger than 32 bits and subvariables can not be written.

- Processor register r1 contains the base address number of the variableto be written.

- r2 species the rst register that is to be transferred to the variable, seeNote 2 below.

- r3 is the number of indices to be transferred. If r3 = 0 then the entirevariable will be written.

- r4 is the rst used data register in register memory, RM, DR0 - DR23.

- r5 is the last used data register in RM, DR0 - DR23

- IR contains the rst index of the variable to be written.

- PR0 contains a valid pointer (if used).

The parameters r4 and r5 are only used by the register allocation algorithmswithin APS. They do not affect the binary format of the instruction, andhence should not be dened when writng this instruction manually.

c Note:


d Example:

WSII WR0-DR0, WR1; (WR1=5, IR=2, PR0=5)

Five consecutive data registers, DR0-DR4 is transferred to ve variableswith indexes 2, 3, 4, 5, 6 to a variable array in the store. The base addressnumber of the variable array is taken from WR0. The rst data register touse at the transfer is taken from DR0.

e Note 1:

It is only possible to transfer data from data registers (DR0-DR23).

f Note 2:

8/12/2019 Asa Manual 2006







The address of the register to be given in r2 is expressed as the normalregister address dened in the document ’ASA201C, assembler instructionparameters’. DR0 has the address 6, DR1 has the address 7 and so on.DR23 has the address 29.

3.5 WSS, Write Subvariable in Store

a Format:

WSS var/vln-r;

b Function:

The contents of process register r are transferred to a subvariable withinthe composite variable var in the store.

The subvariable is pointed out with its size in bit vl and with its sequencenumber n.

The vl right-hand bits in register r are stored in the indicated subvariable.The rest of the contents in the variable remain unchanged.

c Example:

WSS CLINK/H9-WR5;

The 8 least signicant bits in process register WR5 are transferred to thesubvariable which corresponds to half-word 9 within the composite variableCLINK.

d Implementation:

The assembler instruction WSS generates one of the machine operationsWSSU or WSSL. WSSU will be generated if the base address of var is1-255, else WSSL will be generated.

3.6 WHC, Write Halfword Constant

a Format:

WHC var-h;

b Function:

The half-word constant h is transferred right-justied to a variable var in thedata store.

The variable var is cleared to zero before the transfer. If the variable isless than 8 bits, that part of h which cannot be contained in the variable istruncated from the left.

8/12/2019 Asa Manual 2006







c Example:

WHC TIMER-36;

The numeric value 36 is stored in variable TIMER.

d Implementation:

The assembler instruction WHC generates one of the machine operationsWHCU or WHCL. WHCU will be generated if the base address of var is1-255, else WHCL will be generated.

3.7 WZ, Write Zeros

a Format:

WZ var;

b Function:

Transfer of zeros to variable var in the data store.

c Example:

WZ ATIME;

Variable ATIME is cleared to 0.

d Implementation:

The assembler instruction WZ generates one of the machine operationsWZU or WZL. WZU will be generated if the base address of var is 1-255,else WZL will be generated.

3.8 WO, Write Ones

a Format:

WO var;

b Function:

Transfer of ones to variable var in the data store.

c Example:

WO BTIME;

All bits in variable BTIME are set to 1.

d Implementation:

8/12/2019 Asa Manual 2006







The assembler instruction WO generates one of the machine operationsWOU or WOL. WOU will be generated if the base address of var is 1-255,else WOL will be generated.

3.9 FIRSI, File Insert Register to Store Indexed

a Format:

FIRSI var-r1, r2;

b Function:

The instruction transfers the contents of process register r1 up to r1+3 tovariables in a variable array in the store. The pointer has a xed value or isnot used and the index runs consecutively.

The contents of the process registers are placed right-justied in thevariables. If the variables are less than 32 bits, the part of the processregister r1 which cannot be contained in the variables is truncated fromleft. In the case of variables larger than 32 bits, the variable receivesthe contents of process register r1 in the rst 32-bit word, the contentsof process register r1+1 in the second 32-bit word and so on up to thecontents of register r1+3. Subvariables cannot be written.

- IR species the highest index to receiving variable added by 1.

The transfer starts with the value in IR reduced by one. The transfercontinues by decrementing the index value in register IR by 1 until theindex value is equal to the contents of register r2.

- r1 and possibly up to r1+3 species the register contents to be transferredto the variable array of possibly composite variables. The compositevariable might have a size of 2, 4 or 8 16-bit words.

- r2 species the lowest index to receiving variable. The contents of r2are always unaffected.

If the initial value of the contents of register IR is less than or equal to the

contents of register r2, the program continues with the next instruction insequence with unchanged register values.

c Example:

FIRSI 7-WR3, WR9; (WR3=0, IR=8, WR9=0)

The indexed variable with base address 7 is set to zero (WR3) for indexes7 down to 0.

d Additional information:

Instruction is interruptible. If there is an interrupt, the IR register containsthe index to the last receiving variable.

8/12/2019 Asa Manual 2006







e Note:


3.10 WDB, Write in Dynamic Buffer

a Format:

WDB vlb, vl-r;

b Function:

Transfer of data from process register r to a (sub) variable in a dynamicbuffer. If the (sub)variable is smaller than 16 bits, that part of r which is notcontained in the (sub)variable is truncated from the left. Pointer registerPR1 contains a pointer to the buffer. Index register IR contains the indexfor the relevant variable in the buffer. Parameter vl species the length ofthe variable. Parameter vlb is used for specifying a subvariable withinthe indicated variable.

c Example:

WDB C2, W-WR3;

The contents of process register WR3 are transferred to character 2 inthe 16-bit variable indicated by a buffer pointer in register PR1 and anindex in register IR.

d Note 1:


e Note 2:

PR1 should be loaded with instruction RDP if the program will only be usedin APZ models which have RDP implemented.

f Additional information:

Addressing takes place as follows:

The bank’s absolute address WA is read from the base address whosenumber is known to the microprogram. The contents of register(PR1[bit0-11])*2 exp(V+Q) are added to WA. This provides the address to the rstword in the buffer. The address within the buffer to the word which containsthe relevant variable is then calculated with the aid of parameter vl and thecontents of register IR. This address is added to (WA+(PR1[bit 0-11])*2exp(V+Q)). Writing can then take place to the data store. The subvariablewhich is specied by parameter vlm is masked out and changed according

8/12/2019 Asa Manual 2006







to the contents of process register r. The subvariable is then written backinto the data store.

V = 2log (variable length)

Q = 2log (number of variables in array of variables)

3.11 WDBI, Write in Dynamic Buffer Indexed

a Format:

WDBI vlb, vl-r1/vlm, r2,m;

b Function:

Transport of data to a (sub)variable in a dynamic buffer from consecutiveprocess registers.If the register variable is less than 16 bits the data arestored packed in the process registers according to vlm and will be loadedin consecutive index in the variable.

- r1 indicates register for the rst variable.

- vlm species the length and rst position in the register variable.

- vlb species subvariable within the variable.- vl species the length of the variable.

- r2 species the number of variables that shall be transferred.

If r2=0, the instruction does not execute any action.

- m species the maximum number of affected process registersdecremented by one.

If the contents are greater than m+1, software error actions are taken (0<= m <= 63).

- Process register PR1 (bit 0-11) contains pointer to the buffer.

Index register IR contains index to the rst buffer variable.

If the register variable is greater than the (sub)variable the data will betruncated.

If the register variable is smaller than the (sub)variable the receivingvariable will be lled with zeros from most signicant bit.

c Example:

WDBI H0, H-DR0/H0, AR2, 32; (IR=0,AR2=10)

8/12/2019 Asa Manual 2006







To the buffer pointed to by PR1, with the length 8 bits, 10 variables arewritten from process registers. The rst variable is taken from DR0/H0, thesecond variable is taken from DR0/H1, the third from DR1/H0 an so forth.

d Note 1:


e Note 2:


f Note 3:

PR1 should be loaded with instruction RDP.

g Note 4:


3.12 WCB, Write in Communication Buffer

a Format:

WCB var/vlb-r;

b Function:

Transfer of data from process register r to a (sub) variable in aCommunication Buffer. Parameter var is the base address of the memorybank where the Communication Buffer is allocated.Pointer register PR0contains a pointer to the buffer. Index register IR contains the index forthe relevant variable in the buffer.

If the (sub) variable is smaller than 16 bits, that part of process register rwhich is not contained in the (sub) variable is truncated from the left.

Pointer register PR0 contains a pointer to the buffer. Index register IRcontains the index for the relevant variable in the buffer.

The Communication Buffer variable size is dened by Base Address Tablefor memory bank. Default variable size is 16 bits. Larger variables than 16bits can not be used.

Parameter vlb is used for specifying a subvariable within the indicatedvariable.

c Note:


8/12/2019 Asa Manual 2006







3.13 CCBI, Copy Communication Buffer Indexed

a Format:

CCBI hc, t, r;

b Function:

The instruction transfers a block of data from a communication buffer tothe same or different Communication Buffer, or clears a block of data in aCommunication Buffer.

The indicated pointer register(s) contains a pointer to the buffer(s). Theindicated index register(s) contains the start (low) index for the relevantvariable in the buffer(s).

The data block is copyed or cleared starting at the highest index, indexrunning backwards until CR equals zero.

The instruction does not support copying of even-to-odd or odd-to-evenindexes. This means that the difference between ’Index to Copy from’ and’Index to Copy to’ must be even. The compiler will otherwise generatean RCB/WCB loop.

Overlapping indexes are not allowed if copying within a buffer.

Register r points to the rst register where the instruction parameters arestored.

The Communication Buffer variable size is dened by the Base AddressTable for the memory bank. Default variable size is 16 bits.

Subvariable is not allowed.

hc is a reserved constant which should be set to zero.

t = 0 Clear CBt = 1 Copy CBt = 2 Reserved for Move (NOP in this version)t = 3 Reserved for Broadcast (Copy in this version)

CR = Number of W16 to Copy / to Clear. If CR = 0, the instruction isterminated.

r = a1 parameter & pointer to Copy to / to Clearr+1 = Index to Copy to / to Clearr+2 = a2 parameter & pointer to Copy from / not usedr+3 = Index to Copy from / not used

The instruction is interruptable. The data left to be copied is stored inrml[CR]. The other registers are left unchanged.

8/12/2019 Asa Manual 2006







c Data Structure:

Layout of register r and r+2:

31 24 23 22 0

a-par Pointer

d Note:


3.14 WFID, Write Forlopp Identity

a Format:

WFID var;

b Function:

The forlopp indentity (FID) is copied from the register EXECFID to variablevar.Variable var shall have a length of 32 bits. The variable must not bea subvariable.WFID is intended to be used directly after the RETRIEVEstatement.

c Example:

WFID COMMANDFID;

The forlopp indentity is transferred from the register EXECFID to thevariable COMMANDFID.

4 Register Instructions

4.1 LCC, Load Character Constant

a Format:

LCC r-c;

b Function:

Program constant c is transferred to process register r. Constant c isplaced right-justied in r. The rest of r is cleared to zero.

8/12/2019 Asa Manual 2006







c Example:

LCC WR2-8;

Numeric value 8 is stored in process register WR2.

4.2 LHC, Load Halfword Constant

a Format:

LHC r/vlp-h;

b Function:

Halfword constant h is transferred to a variable in process register r. Thelength and location of the variable within the register is specied by vlp.

The storage takes place right-justied in the indicated part of the register.The indicated part of the register is cleared to zero before the transfer.The rest of the contents of process register r remain unchanged with theexception of vlp=H1 and vlp=W0 where r/W1 is cleared to zero.

c Example 1:

LHC WR0/H0-46;

The numeric value 46 is stored in the rst half-word in process registerWR0. The rest of WR0 remain unchanged.

d Example 2:

LHC WR1/W0-46;

The numeric value 46 is stored in the rst half-word of process registerWR1. The rest of WR1 is cleared to zero.

4.3 LWCD, Load Word Constant Double

a Format:

LWCD r/vlr-w;

b Function:

Word constant w is transferred to process register r. The length andlocation of the variable within the register is specied by vlr.

The storage takes place right-justied in the indicated part of the register.The indicated part of the register is cleared to zero before the transfer. Therest of the contents of process register r remain unchanged.

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







r1+2 month

r1+3 day

r1+4 hour

r1+5 minute

r1+6 second

r1+7 decisecond

r1+8 undened

c Example:

LAT WR10;

The contents of process registers will be:

WR10 = undened value

WR11 = year

WR12 = month

WR13 = day

WR14 = hour

WR15 = minute

WR16 = second

WR17 = decisecond

d Note:

That process register WR10 will be undened.

4.6 MFR, Move from Register

a Format:

MFR r1-r2;

b Function:

Transfer of contents of process register r2 to process register r1.

c Example:

8/12/2019 Asa Manual 2006







MFR WR3-WR2;

The contents of process register WR2 are transferred to process registerWR3.

4.7 MFRE, Move from Register Extended

a Format:

MFRE r1-r2/vlm;

b Function:A variable within process register r2 which is indicated by vlm is fetchedand stored right-justied in process register r1. The bits in r1 which are notaffected are cleared to zero.

c Example:

MFRE WR3-WR4/C2;

Character 2 within process register WR4 is stored right-justied in processregister WR3, see the gure below.

C3 C2 C1 C0

WR3 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

>

WR4 0 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0

4.8 MTR, Move To Register

a Format:

MTR r1/vlm-r2;b Function:

The vl right-hand bits in process register r2 are transferred to a variable inprocess register r1. The position of the variable within r1 is indicated byvlm. Bits in r1 which are not affected are not changed.

c Example:

MTR WR1/C2-WR2;

The four right-hand bits in process register WR2 are transferred tocharacter 2 in process register WR1. See the gure below.

8/12/2019 Asa Manual 2006







C3 C2 C1 C0

WR1 0 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0

<

WR2 0 1 0 0 1 1 1 1 0 1 0 1 1 0 1 0

a

Only the 4 least signicant bits in WR2 in the example will be transferred toprocess register WR1.

4.9 TNB , Translate Number to Bit vector

a Format:

TNB r1-r2;

b Function:

A numeral is fetched from bit 0-4 of register r2.

The bit in r1 with that number is set. All other bits in r1 are cleared.

c Example:

TNB WR7-AR1;

register before: WR7=H’22FF, AR1=H’3401

register after: WR7=H’0002, AR1=H’3401

Since AR1 B0-B3 have the value 1, B1 is set in WR.

4.10 CFID, Clear Forlopp Identitya Format:

CFID ;

b Function:

The forlopp identity register (EXECFID) is cleared.CFID is intended to beused by the operating system when the EXECFID register is to be cleared.

c Example:

CFID ;

8/12/2019 Asa Manual 2006







The contents of register EXECFID is cleared.

4.11 TFID, Test Forlopp Identity

a Format:

TFID var;

b Function:

A check is done that the forlopp indentity (FID) which is stored in variable

var is the same as in register EXECFID. If it is not, a check is done if theFORLOPP identities are joined (join information is fetched from variablesin the FORLOPP changes). If the FORLOPP identities are NOT joinedsoftware recovery actions will be taken.TFID is intended to be used directlyafter ENTER statements in order to insure that received signals are partof the current forlopp.

c Example:

TFID COMMANDFID;

If the contents of variable COMMANDFID and register EXECFID areidentical, then normal program execution will continue. If they are not, andthey are not joined, software recovery actions will be taken. That is signalPROGERROR will be sent on priority level TRL and the current job maypossibly be aborted.

5 Arithmetic Instructions

5.1 AR, Add Register to Register

a Format:

AR r1-r2;

b Function:

The contents of process register r2/W0 are added to the contents ofprocess register r1/W0. If the result of the addition can be contained inr1/W0, result indicator RIR is set to zero. If the result requires a larger eldlength, carry is obtained and RIR is then set to one.

The result is stored right-justied in register r1/W0. If the result cannot becontained in the register it will be truncated from the left.

c Example:

AR AR0-AR1;

8/12/2019 Asa Manual 2006







The contents of process register AR1/W0 are added to the contents ofprocess register AR0/W0.

5.2 ARD, Add Register to Register Double

a Format:

ARD r1-r2;

b Function:

The contents of process register r2 is added to the contents of processregister r1. If the result of the addition can be contained in r1, resultindicator RIR is set to zero. If the result requires a larger eld length, carryis obtained and RIR is then set to one.

The result is stored right-justied in register r1. If the result cannot becontained in the register it will be truncated from the left.

c Example:

ARD AR0-AR1;

The contents of process register AR1 are added to the contents of processregister AR0.

5.3 ACC, Add Character Constant To Register

a Format:

ACC r-c;

b Function:

Program constant c is added to the contents of process register r/W0.r/W1 is set to zero.

If the result of the addition can be contained in register r/W0, resultindicator RIR is cleared to zero. If, on the other hand, the result requires alarger eld length, carry occurs and RIR is then set to one.

The result is stored right-justied in register r/W0. If the result has a largereld length in r/W0, the result is truncated from the left.

c Example:

ACC AR0-3;

The number 3 is added to the contents of process register AR0/W0.

8/12/2019 Asa Manual 2006







5.4 AWC, Add Word Constant to register

a Format:

AWC r-w;

b Function:

Program constant w is added to the contents of process register r/W0. Ifthe result of the addition can be contained in r/W0, result indicator RIR isreset to zero. If the result requires a larger eld length, carry occurs andRIR is set to one.

The result is stored right-justied in register r. The 16 most signicantbits are cleared.

c Example:

AWC AR0-65535;

Number 65535 is added to the contents of process register AR0/W0.

5.5 AWCD, Add Word Constant To Register Double

a Format:

AWCD r-w;

b Function:

Program constant w is added to the contents of process register r.

If the result of the addition can be contained in register r, result indicatorRIR is cleared to zero. If, on the other hand, the result requires a largereld length, carry occurs and RIR is then set to one.

The result is stored right-justied in register r. If the result has a larger eldlength in r, the result is truncated from the left.

c Example:

AWCD AR0-3;

The number 3 is added to the contents of process register AR0. 32 bitsare affected.

5.6 AHCS, Add Halfword Constant To Store

a Format:

AHCS var-h;

8/12/2019 Asa Manual 2006







b Function:

The program constant h is added to a variable var in the store.

The instruction is carried out correctly for variables with a maximum eldlength of 32 bits.

If the variable should have a size exceeding 32 bits, only the 32 leastsignicant bits of the variable participate in the addition.

If the result of the addition can be contained in the variable or in the 32least signicant bits of the variable, result indicator RIR is cleared to zero.The result is stored right-justied in the variable. If, on the other hand, theresult cannot be contained in the variable, carry will occur, in which caseRIR is set to one. The result is truncated from the left with a number of bitswhich cannot be contained in the variable.

c Example:

AHCS COUNT-136;

The number 136 is added to the variable COUNT.

d Implementation:

The assembler instruction AHCS generates one of the machine operationsAHCSU or AHCSL. AHCSU will be generated if the base address of var is1-255, else AHCSL will be generated.

5.7 SR, Subtract Register from Register

a Format:

SR r1-r2;

b Function:

The contents of process register r2/W0 is subtracted from the contents ofprocess register r1/W0. If the result of the subtraction is greater than orequal to 0, result indicator RIR is cleared to zero. If, on the other hand, theresult is smaller than 0, carry will occur and RIR is then set to one.

Note that the machine only processes positive integers. A negative result isstored in the form of the two-complement to the numeric value of the result.

c Example:

SR AR1-AR2;

The contents of process register AR2 are subtracted from the contents ofprocess register AR1.

8/12/2019 Asa Manual 2006







5.8 SRD, Subtract Register from Register Double

a Format:

SRD r1-r2;

b Function:

The contents of process register r2 is subtracted from the contents ofprocess register r1. If the result of the subtraction is greater than or equalto zero, the result indicator RIR is reset to zero.If, on the other hand, the

result is smaller than zero, carry occurs and RIR is set to one.Note that the machine only processes positive integers. A negative result isstored in the form of the two-complement to the numeric value of the result.

c Example:

SRD AR1-AR2;

The contents of process register AR2 are subtracted from the contents ofprocess register AR1.

5.9 SCC, Subtract Character Constant from Register

a Format:

SCC r-c;

b Function:

Program constant c is subtracted from the contents of process registerr/W0. r/W1 is set to zero.

If the result of the subtraction is greater than or equal to 0, result indicatorRIR is cleared to zero.

If, on the other hand, the result is smaller than 0 carry will occur and RIR isthen set to one.


c Example:

SCC AR1-5;

The number 5 is subtracted from the contents of process register AR1/W0.

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







The number 5 is subtracted from the contents of process register AR1.32 bits are affected.

5.12 SHCS, Subtract Halfword Constant from Store

a Format:

SHCS var-h;

b Function:

Program constant h is subtracted from a variable var in the store. Theinstruction is carried out correctly for variables with the maximum eldlength of 32 bits.

If the variable should have a size exceeding 32 bits, only the 32 leastsignicant bits of the variable participate in the subtraction.

If the result of the subtraction is greater than or equal to 0, result indicatorRIR is cleared to zero.

If, on the other hand, the result is smaller than 0, carry will occur and RIRis then set to one.


c Example:

SHCS COUNT-#8B;

The hexadecimal number 8B is subtracted from variable COUNT.

d Implementation:

The assembler instruction SHCS generates one of the machine operationsSHCSU or SHCSL. SHCSU will be generated if the base address of var is1-255, else SHCSL will be generated.

5.13 MR, Multiply Register

a Format:

MR r1-r2;

b Function:

The contents of process registers r1/W0 and r1+1/W0 are regarded as one32-bit binary number with the most signicant bits in r1+1. The contents ofprocess registers r2/W0 and r2+1/W0 is regarded as another 32-bit binarynumber with the most signicant bits in r2+1. These two numbers are

8/12/2019 Asa Manual 2006







multiplied and the 32 least signicant bits of the result are stored in r1/W0and r1+1/W0 with the least signicant bits in r1. r1/W1 and r1+1/W1 arecleared to zero. RIR is cleared to zero if the result can be contained in 32bits, otherwise RIR is set to one.

c Example:

MR AR0-AR2;

The contents of process registers AR0 and AR1 are multiplied by AR2 andAR3 and the result is stored in AR0 and AR1.

Note, r1 and r2 may not be temporary variables.

5.14 DR, Divide Register

a Format:

DR r1-r2;

b Function:

The contents of process registers r1/W0 and r1+1/W0 are regarded as one32-bit binary number with the most signicant bits in r1+1. The contents ofprocess registers r2/W0 and r2+1/W0 is regarded as another 32-bit binarynumber with the most signicant bits in r2+1. The contents of r1 and r1+1are divided by the contents of r2 and r2+1.The result is stored in r1/W0 andr1+1/W0 with the least signicant bits in r1. The remainder (modulo) isstored in r1+2/W0 and r1+3/W0 with the least signicant bits in r1+2. Bits16-31 of r1, r1+1, r2 and r2+1 are cleared to zero.Program handling erroractions are initiated at attempts to divide by zero.

c Example:

DR AR0-AR3;

The contents of process register AR0 and AR1 are divided by the contentsof register AR3 and WR0 and the result is stored in AR0 and AR1. Theremainder is stored in AR2 and AR3.

Note, r1 and r2 may not be temporary variables.

6 Shift and Logical Instructions

6.1 SHL, SHift Left

a Format:

SHL r, z;

8/12/2019 Asa Manual 2006







b Function:

A shift of B15-B0 in process register r to the left the number of stepsspecied by program constant z. Zeroes are entered from the right.B31-B16 do not participate in the operation and are set to zero before theresult is stored in r.

If z has the value zero, the number of shift steps will be fetched from indexregister IR, character 0.

RIR is set to one if any of bits shifted out from B15 is one. Otherwise RIRis reset to zero.

c Example:

SHL AR0, 5;

The contents of process register AR0 are shifted 5 steps to the left.

If the contents were H’1FFF before, they become H’FFE0 afterwards andRIR=1.

6.2 SHLD, SHift Left Double

a Format:

SHLD r, x;

b Function:

A shift of the contents of the process register r to the left the number ofsteps specied by x. Zeroes are entered from the right. If x has the valuezero, the number of shift steps will be fetched from index register IR B4-B0.

RIR is set to one if any of the bits shifted out is one. Otherwise RIR isreset to zero.

c Example:

SHLD AR1, 24;

The contents of process register AR1 are shifted 24 steps to the left.

If the contents of AR1 were H’1FFFF before, they become

H’FF00 0000 afterwards and RIR=1.

6.3 SHR, SHift Right

a Format:

8/12/2019 Asa Manual 2006







SHR r, z;

b Function:

Shift B15-B0 in process register r to the right the number of steps speciedby program constant z. Zeroes are entered from the left. B31-B16 donot participate in the operation and are set to zero before the result isstored in r.

If z has the value zero, the number of shift steps will be fetched from indexregister IR, character 0.

RIR is set to one if any of the bits shifted out from B0 is set to one.Otherwise RIR is reset to zero.

c Example:

SHR AR0, 3;

The contents of process register AR0 are shifted 3 steps to the right. Ifthe contents of AR0 were H’1FFF before, they become H’3FF afterwardsand RIR=1.

6.4 SHRD, SHift Right Double

a Format:

SHRD r, x;

b Function:

A shift of the contents of process register r to the right the number of stepsspecied by x. Zeroes are entered from the left. If x has the value 0, thenumber of shift steps will be fetched from index register IR B4-B0. RIR isset to one if any of the bits shifted out is not equal to zero. OtherwiseRIR is reset to zero.

c Example:

SHRD AR0, 12;

The contents of process register AR0 are shifted 12 steps to the right.

If the contents of AR0 were H’1FFF0000 before, they become H’0001FFF0afterwards and RIR=0.

6.5 ROL, ROtate Left

a Format:

ROL r, z;

8/12/2019 Asa Manual 2006







b Function:

Rotation of B15-B0 in process register r to the left the number of stepsspecied by program constant z. B31-B16 do not participate in theoperation and are cleared before the result is stored in r.

If z has the value zero, the number of shift steps shall be fetched fromindex register IR, character 0.

RIR is set to one if any of the bits which have been shifted out are set toone. Otherwise RIR is reset to zero.

c Example:

ROL AR0, 4;

If AR0 = H’1234 before the execution of ROL, AR0 will contain H’2341 afterthe execution of ROL. RIR is set to one.

6.6 ROLD, ROtate Left Double

a Format:

ROLD r, x;

b Function:

Rotation of B31-B0 in process register r to the left the number of stepsspecied by program constant x.

If x has the value 0, the number of shift steps is specied by index registerIR B4-B0. RIR is set to one if any of the bits which have been shifted out isset to one. Otherwise RIR is reset to zero.

c Example:

ROLD AR0, 16;

If AR0 = H’123400CD before the execution of ROLD, AR0 will containH’00CD1234 after the execution of ROLD. RIR is set to one.

6.7 ROR, ROtate Right

a Format:

ROR r, z;

b Function:

8/12/2019 Asa Manual 2006







Rotation of B15-B0 in process register r to the right the number of stepsspecied by program constant z. B31-B16 do not participate in theoperation and are cleared before the result is stored in r.

If z has the value zero, the number of shift steps shall be fetched fromindex register IR, character 0.

RIR is set to one if any of the bits shifted out is set to one. OtherwiseRIR is reset to zero.

c Example:

ROR AR3, 4;

If AR3 = H’ABCD before the execution of ROR, AR3 will contain H’DABCafter the execution. RIR is set to one.

6.8 RORD, ROtate Right Double

a Format:

RORD r, x;

b Function:

Rotation of B31-B0 in process register r to the right the number of stepsspecied by program constant x. If x has the value zero, the number ofshift steps is specied by index register IR B4-B0.

RIR is set to one if any of the bits shifted out is set to one. OtherwiseRIR is reset to zero.

c Example:

RORD AR0, 8;

If AR3 = H’1234ABCD before RORD is executed, AR3 will containH’CD1234AB after RORD is executed. RIR is set to one.

6.9 ER, Exclusive or in Register

a Format:

ER r1-r2;

’Exclusive OR’ is carried out between the contents of process registers r1and r2 and the result is stored in r1.

32 bits are affected.

Each bit of r1 is changed in accordance with the following truth table:

8/12/2019 Asa Manual 2006







r1

0 1

r2 0 0 1

1 1 0

a

Result indicator RIR is reset to zero if the result is zero and is set to one ifthe result is not zero.

b Example:

ER AR1-AR2;

A logical ’exclusive OR’ is carried out between the contents of processregisters AR1 and AR2. The result is stored in AR1.

6.10 OR, Logical Or in Register

a Format:

OR r1-r2;

b Function:

A logical ’OR’ is carried out between the contents of process registers r1and r2. The result is stored in r1. 32 bits are affected. Each bit of r1 ischanged in accordance with the following truth table:

r1

0 1

r2 0 0 1

1 1 1

a

The result indicator RIR is reset to zero if the result is zero and is set toone if the result is not zero.

b Example:

OR AR2-AR0;

8/12/2019 Asa Manual 2006







A logical ’OR’ is carried out between the contents of process registers AR2and AR0. The result is stored in AR2.

6.11 NR, Logical and in Register

a Format:

NR r1-r2;

b Function:

A logical ’AND’ is carried out between the contents of process registers r1and r2. 32 bits are affected. The result is then stored in process register r1.

Each bit in r1 is changed in accordance with the following truth table:

r1

0 1

r2 0 0 0

1 0 1

a

Result indicator RIR is reset to zero if the result is zero and is set to one ifthe result is not zero.

b Example:

NR AR1-AR3;

A logical ’AND’ is carried out between the contents of process registersAR1 and AR3. The result is stored in AR1.

6.12 NWC, Logical and with Word Constant

a Format:

NWC r-w;

b Function:

A logical ’AND’ is carried out between program constant w and thecontents of process register r. The result is stored in the process register.32 bits are affected.

Each bit in r is changed in accordance with the following truth table:

8/12/2019 Asa Manual 2006







r

0 1

w 0 0 0

1 0 1

a

Result indicator RIR is cleared if the result is zero and is set to one if theresult is not zero.

b Example:

NWC AR3-H’D4;

Logical ’AND’ is carried out between hexadecimal number 00D4 and thecontents of process register AR3.

7 Local Jump Instructions

The local jump instructions are implemented with machine operations withparameter n, which species the instruction address at program label l to whichthe jump is to take place. When the jump takes place, n is entered in the IARregister. In the case of condition jump instructions, if the jump is not to beexecuted, IAR is stepped to the next instruction. PSA remains unchanged inthe case of local jumps.

Comparisons in conditional jump instructions are done with 32 bits.

7.1 JLN, Jump Local Normal

a Format:

JLN l;

b Function:

An unconditional jump is done to a program label l within the samesoftware unit.

c Example:

JLN START;

An unconditional jump to program label START.

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







JZR in;

A jump is done to program label in if RIR has the value zero.

7.5 JEC, Jump on Equality with Character Constant

a Format:

JEC r, c, l;

b Function:

If the contents of process register r are equal to program constant c, a jumpis done to a program label l within the same software unit. Otherwise theexecution continues with the next instruction in sequence.

c Example:

JEC WR1,6, TEST;

A jump is done to program label TEST if process register WR1 containsthe number 6.

7.6 JUC, Jump on Unequality with Character Constanta Format:

JUC r, c, l;

b Function:

If the contents of process register r and program constant c have differentvalues, a jump is done to a program label l within the same software unit.Otherwise the execution continues with the next instruction in sequence.

c Example:

JUC WR3, 12, OUT;

A jump is done to program label OUT if process register WR3 containsany value other than the number 12.

7.7 JER, Jump on Equality between Registers

a Format:

JER r, l;

b Function:

8/12/2019 Asa Manual 2006







If process registers r and CR contain equal values, a jump is done to aprogram label l within the same software unit. Otherwise the executioncontinues with the next instruction in sequence.

c Example:

JER WR4, EQ;

A jump is done to program label EQ if the contents of process registersWR4 and CR are equal.

7.8 JUR, Jump on Unequality between Registers

a Format:

JUR r, l;

b Function:

If the contents of process registers r and CR are unequal, a jump is doneto a program label l within the same software unit. Otherwise the executioncontinues with the next instruction in sequence.

c Example:

JUR WR0, UQ;

A jump is done to program label UQ if the contents of process registersWR4 and CR are not equal.

7.9 JGT, Jump on Greater Than

a Format:

JGT r, l;

b Function:

If the value of process register r is greater than the value of process registerCR, a jump is done to a program label l within the same software unit.Otherwise the execution continues with the next instruction in sequence.

c Example:

JGT WR0, BEGIN;

A jump is done to program label BEGIN if the contents of process registerWR0 are greater than the contents of CR.

8/12/2019 Asa Manual 2006







7.10 JLT, Jump on Less Than

a Format:

JLT r, l;

b Function:

If the value of process register r is less than the value of process registerCR, a jump is done to a program label l within the same software unit.Otherwise the execution continues with the next instruction in sequence.

c Example:

JLT WR9, ROUTINE

A jump is done to program label ROUTINE if the contents of processregister WR9 are less than the contents of process register CR.

7.11 JTR, Jump on Table Indexed by Register

a Format:

JTR r, h;

b Function:

A jump is done in accordance with the following jump table, in whichthe relevant position in the table is specied by a jump index in processregister r.

The instruction is accompanied by an address to an error label and then bya jump table embracing a number of jump addresses. Program constanth species the maximum jump index. The maximum value for h is equalto 255. All jump addresses are supplied by means of macro-instructionADDR.

If the contents of process register r are greater than program constant h,an error exit takes place in accordance with the address which has beenstored immediately after the instruction.

c Example:

JTR WR6, 2;ADDR ERROR;ADDR WHEN_VAL_0;ADDRWHEN_VAL_1;ADDR WHEN_VAL_2;

If process register WR6 contains the value 0, a jump takes place toprogram label WHEN_VAL_0.

If WR6 contains the value 1, a jump takes place to program labelWHEN_VAL_1.

8/12/2019 Asa Manual 2006







If WR6 contains the value 2, a jump takes place to program labelWHEN_VAL_2.

If WR6 contains a value greater than 2, a jump takes place to programlabel ERROR.

7.12 JTS, Jump on Table Indexed by Store

a Format:

JTS var, h;

b Function:

A jump is done in accordance with the following jump table in which therelevant position in the table is specied by a jump index in variable var.

The instruction is accompanied by an address to an error label and then bya jump table embracing a number of jump addresses. Program constant hspecies the maximum jump index. The maximum value for h is equal to255. All jump addresses are supplied by means of macro instruction ADDR.

If the contents of variable var are greater than program constant h, an errorexit takes place in accordance with the address which has been storedimmediately after the instruction.

The variable has a maximum length of 32 bits.

c Example:

JTS COUNT, 2;ADDR ERROR;ADDR WHEN_VAL_0;ADDRWHEN_VAL_1;ADDR WHEN_VAL_2;

If the variable COUNT contains the value 0, a jump takes place to programlabel WHEN_VAL_0.

If COUNT contains the value 1, a jump takes place to program label

WHEN_VAL_1.

If COUNT contains the value 2, a jump takes place to program labelWHEN_VAL_2.

If COUNT contains a value greater than 2, a jump is done to programlabel ERROR.

d Implementation:

The assembler instruction JTS generates one of the machine operationsJTSU or JTSL. JTSU will be generated if the base address of var is 1-255,else JTSL will be generated.

8/12/2019 Asa Manual 2006







8 Signal Transmission Instructions

8.1 SSN, Send Signal Normal

a Format:

SSN sig;

b Function:

Signal sig is sent to a block and carries a pointer and data. ’Signal sending

pointer’ (ssp) and data format (f) are specied by sig. Each transferreddata is 32 bits.

c Example:

SSN SEIZE;

Signal SEIZE is sent to the receiving block specied in the signal. Thesignal carries a pointer and data according to the format.


- SSN can be used to send signals to active or passive blocks.- The globalsignal number (gsn) is fetched from the signal sending table (sst) of thesending block. The block number and the local signal number (lsn) of thereceiver of the signal is then fetched from the global signal distributiontable for unique signal (GSDT-U).- Start of execution in receiving block onaddress PSA + IA. PSA is fetched from the reference table of the receivingblock and IA is fetched from position lsn in the signal distribution table ofthe receiving block.

8.2 SSIN, Send Signal Indirect Normal

a Format:

SSIN r, sig;

b Function:

Signal sig is sent to a block carrying a pointer and data. The signal sendingpointer (ssp) and data format (f) are specied by sig while the blockreference is specied in register r. Each transferred data is 32 bits.

c Example:

SSIN WR1, SEIZE;

Signal SEIZE is sent to a block. Register WR1 species the blockreference. A pointer and data accompany the signal according to theformat.

8/12/2019 Asa Manual 2006







d Note:

SSIN works the same way as SSN with the difference that the blocknumber is calculated from the block reference stored in register r and thatthe local signal number (lsn) of the receiver is fetched from the global signaldistribution table for multiple signals (GSDT-M). The register contents afterSSIN are the same as after SSN.

8.3 SSPD, Send Signal from Process Register Direct

a Format:

SSPD r;

b Function:

A signal is sent to a block carrying a pointer and data. The signal headerinformation is fetched from process registers by SSPD. Receiving block isfetched from register r. Local signal number and data format are fetchedfrom register r+1. Transmitting block number is fetched from register r+2.The pointer and the data are stored in the PR0 register and DR registersrespectively before SSPD. Each transferred data is 32 bits.

Input data to SSPD:

15 12 11 4 3 0

0 bn-r r

lsn f r+1

0 bn-s r+2

a Example:

SSPD WR7;

A signal in accordance with WR7, WR8 and WR9 is sent to the blockspecied in WR7. The number of data items is in accordance with theformat in WR8/C0.

SSPD can be used to send a signals to active or passive blocks.

The instruction executes the following:

- SR0 and SR1 are loaded with information.

- Program execution is started in the receiving block on address PSA+IA.PSA is fetched from the reference table of the receiving block and IA is

8/12/2019 Asa Manual 2006







fetched from position LSN in the’ signal distribution table of the receivingblock.

b Note:


8.4 SSL, Send Signal and Link

a Format:

SSL sig;

b Function:

The address to the next instruction in sequence is stored together with thecurrent block number in the link register stack.

Signal sig is then sent to the destination block carrying a pointer and data.The signal sending pointer (ssp) and data format (f) are specied by sig.Each transferred data is 32 bits.

c Example:

SSL SEIZE;

Signal SEIZE is sent with linkage to the receiver block specied in thesignal. A pointer and data accompany the signal according to the format.

d Implementation:

As for SSN with the addition that the address to the next instruction insequence is stored in the link register stack. The block number andinstruction address are stored.

e Note:

No process registers (temporary variables) are saved.

8.5 SSIL, Send Signal Indirect and Link

a Format:

SSIL r, sig;

b Function:

The address to the next instruction in sequence is stored in the link registerstack together with the current block number.

8/12/2019 Asa Manual 2006







Signal sig is then sent to a block in its own processor, carrying a pointerand data. The signal sending pointer (ssp) and data format (f) are speciedby sig while the block reference is specied in register r. Each transferreddata is 32 bits.

c Example:

SSIL WR1, SEIZE;

Signal SEIZE is sent to a block. Register WR1 species the blockreference. A pointer and data accompany the signal in accordance withthe format.

d Note:


e Implementation:

SSIL is implemented in the same way as SSL with the difference that theblock number is calculated from the block reference in register r and thatthe local signal number (lsn) of the receiver is fetched from the globalsignal distribution table for multiple signals (GSDT-M).

8.6 SSPL, Send Signal from Process register Linkeda Format:

SSPL r;

b Function:

The address to the next instruction in sequence is stored together with thecurrent block number in the link register stack.

A signal carrying a pointer and data is then sent to a block. The signalheader information is fetched from process registers by SSPL. Receivingblock is fetched from register r. Local signal number and data formatare fetched from register r+1. Transmitting block number is fetched fromregister r+2. The pointer and the data are stored in the PR0 and DRregisters respectively before SSPL. Each transferred data is 32 bits.

c Example:

SSPL WR20;

A signal in accordance with WR20, WR21 and WR22 is sent with linkageto the block specied in WR20. The number of data items is in accordancewith the format in WR21/C0.

d Note:

8/12/2019 Asa Manual 2006








e Implementation:

As for SSPD with the addition that the address to the next instruction insequence is stored in the link register stack (block number and instructionaddress). Note that process registers (temporary variables) are not saved.

8.7 SSB, Send Signal via Job Buffer

a Format:

SSB sig;

b Function:

A signal message containing signal sig including pointer, data and forloppidentity, is inserted in a job buffer in own processor. The relevant job buffer(jb), signal sending pointer (ssp) and the data format (f) are specied bysig. Pointer and data are fetched from the pointer register PR0 and thedata registers DR0- DR23 respectively. The forlopp identity is fetched fromregister EXECFID. Each transferred data is 16 bits. The current forloppidentity stored in register EXECFID is also transferred in the signal.

c Example:

SSB IDLE;

A signal message is entered in a job buffer. The signal message containssignal IDLE with a pointer and data in accordance with the format. Thesignal also contains the forlopp identity of the current forlopp.

8.8 SSBD, Send Signal via Job Buffer Double

a Format:

SSBD sig;

b Function:

A signal message containing signal sig including pointer, data and forloppidentity, is inserted in a job buffer in own processor. The relevant job buffer(jb), signal sending pointer (ssp) and the data format (f) are specied bysig. Pointer and data are fetched from the pointer register PR0 and thedata registers DR0- DR23 respectively. The forlopp identity is fetched fromregister EXECFID. Each transferred data is 32 bits. The current forloppidentity stored in register EXECFID is also transferred in the signal.

c Example:

SSBD IDLE;

8/12/2019 Asa Manual 2006







A signal message is entered in a job buffer. The signal message containssignal IDLE with a pointer and data in accordance with the format. Thesignal also contains the forlopp identity of the current forlopp.

8.9 SSIB, Send Signal Indirect via Job Buffer

a Format:

SSIB r, sig;

b Function:

A signal message containing signal sig including pointer, data and forloppidentity, is inserted in a job buffer in own processor. The relevant job buffer(jb), signal sending pointer (ssp) and data format (f) are specied by sig,while the block reference is specied in register r. Pointer and data arefetched from the pointer register PR0 and the data registers DR0-DR23respectively. Each transferred data is 16bits. The current forlopp identitystored in register EXECFID is also transferred in the signal.

c Example:

SSIB WR3, CLEAR; A signal message is entered in a job buffer. The signalmessage contains signal CLEAR with a pointer and data in accordance

with the format. The forlopp identity is also sent in the signal. The blockreference of the receiver to the signal is fetched from register WR3.

d Implementation:

SSIB is implemented in the same way as SSB but with the difference thatthe block number is calculated from the block reference in register r.

8.10 SSIBD Send Signal Indirect via Job Buffer Double

a Format:

SSIBD r, sig;

b Function:

A signal message containing signal sig including pointer, data and forloppidentity, is inserted in a job buffer in own processor. The relevant job buffer(jb), signal sending pointer (ssp) and data format (f) are specied by sig,while the block reference is specied in register r. Pointer and data arefetched from the pointer register PR0 and the data registers DR0-DR23respectively. The forlopp identity is fetched from register EXECFID. Eachtransferred data is 32 bits. The current forlopp identity stored in registerEXECFID is also transferred in the signal.

c Example:

8/12/2019 Asa Manual 2006







SSIBD WR3, CLEAR;

A signal message is entered in a job buffer. The signal message containssignal CLEAR with a pointer and data in accordance with the format.The forlopp identity is also sent in the signal. The block reference of thereceiver to the signal is fetched from register WR3.

d Implementation:

SSIBD is implemented in the same way as SSBD but with the differencethat the block number is calculated from the block reference in register r.

8.11 SCBS, Send Combined Backward Signal

a Format:

SCBS sig;

b Function:

The address to the next instruction in sequence and the receiving block’snumber are taken from the link register stack.

Signal ’sig’ is then sent to the block in accordance with the link register

stack, carrying a pointer and data.

A position in SST must be occupied to be able to set the tracebit for thissignal. 32 bits are transferred for each data.

c Example:

SCBS RET1;

Signal RET1 is sent back according to a block number and instructionaddress which are fetched from the link register stack.


This instruction has been introduced to permit tracing on combinedbackward signals. It is implemented in the same way as EP global linkedreturn jump with the addition that a reference is done to the signal sendingtable.

e Note:

SCBS is not be generated by APS at present.

8.12 RCBS, Retrieve Combined Backward Signal

a Format:

8/12/2019 Asa Manual 2006







RCBS sig;

b Function:

This instruction has no operative function. It has been included to permittracing on the reception of a combined backward signal. 32 bits aretransferred for each data.

c Example:

RCBS RET1;

The signal RET1 is received.

d Note 1:

A position in SDT must be occupied to be able to set the tracebit for thissignal.

e Note 2:

RCBS is not generated by APS at present.

8.13 SSPB, Send Signal from Process Register via Job Buffer

a Format:

SSPB r;

b Function:

A signal message with pointer and data is inserted in the job bufferindicated in register r. The entire signal message is fetched from processregisters; receiving block from register r+2, local signal number and dataformat from register r+3, transmitting processor and block from registerr+4 and the pointer and data from the PR0 register and DR registersrespectively. Each transferred data is 16 bits. The current forlopp identitystored in register EXECFID is also transferred in the signal.

Input data to SSPB:

8/12/2019 Asa Manual 2006







15 0

0 jb r

not used r+1

0 bn-r r+2

lsn f r+3

0 bn-s r+4

a Example:

SSPB WR13;

A signal in accordance with WR15, WR16 and WR17 is sent to a block(WR15). The job buffer is specied in WR13 and the number of data itemsin the signal is indicated by f in WR16/C0.

b Note 1:


c Note 2:

SSPB is the same assembler instruction as the older SIPBO.

8.14 SSPBD Send Signal from Process Registers via Job BufferDouble

a Format:

SSPBD r;

b Function:

A signal message with pointer and data is inserted in the job bufferindicated in register r. The entire signal message is fetched from processregisters; receiving block from register r+2, local signal number and dataformat from register r+3, transmitting processor and block from registerr+4 and the pointer and data from the PR0 register and DR registersrespectively. Register r+1 is not used. Each transferred data is 32 bits.The current forlopp identity stored in register EXECFID is also transferredin the signal.

Input data to SSPBD:

8/12/2019 Asa Manual 2006







15 0

0 jb r

not used r+1

0 bn-r r+2

lsn f r+3

0 bn-s r+4

a Example:

SSPBD WR13;

A signal in accordance with WR15, WR16 and WR17 is sent to a block(WR15). The job buffer is specied in WR13 and the number of data itemsin the signal is indicated by f in WR16/C0.

b Note:


8.15 XSTQ, Send Signal via Time Queue

a Format:

XSTQ r;

b Function:

A signal is entered in a central time queue for a specied time delay. Theaddress to which the signal is sent can either be its own block or anotherblock. Each transferred data is 32 bits.

There are four time queues, TQA, TQB, TQC and TQC. TQA is an absolutetime queues, the others are relative. The characteristics are:

c TQA

The month is specied with the gures 0-12. The day is specied with thegures 0-31. If 0 is specied for the month, the signal is delayed until thespecied day, hour and minute occurs. The corresponding procedure isadopted if the day = 0.

d TQB

100 ms long time intervals.

8/12/2019 Asa Manual 2006







e TQC

1 s long time intervals.

f TQD


Input data for the instruction is fetched from register r and subsequentregisters.

TQA15 12 11 9 8 4 3 2 1 0

stype=0 bn-r r

ssp f r+1

0 tq jb r+2

month day r+3

hour minute r+4

TQB, TQC, TQD15 12 11 9 8 4 3 1 2 0

stype=0 bn-r r

ssp f r+1

0 tq jb r+2

number of time intervals r+3

a

When XRST is used in macro the following applies:bn-r is zero for uniquesignals.bn-r is not equal to zero for multiple signals.

ssp is the position in the signal sending table in the block for the signalto be sent.

b Example:

TQINF WR0-RMWDEL, 2;LCC WR3-5;XSTQ WR0;

8/12/2019 Asa Manual 2006







Signal RMWDEL is sent via the time queue. The macro TQINF is used toload the register WR0 and onwards with required data. Signal RMWDEL issent with a delay of 5 to 6 seconds. The data to send in the signal is takenfrom the of DR-registers previously loaded.

c Note 1:


d Note 2:

Registers r, r+1 and r+2 can be loaded with the aid of macros TQINF orTQINFI.

e Note 3:

The delay in the relative time queues will be at least the nominal time. Themaximum delay is the nominal time plus the ’delay unit’ of the time queue.E.g. a nominal delay of 5 seconds in TQC will in reality be between 5 and 6seconds. The maximum delay is 65534 time units.

f Note 4:

The signal from Time Queue will be executed with a SSPB or SSPBD inblock JOB.

8.16 XSTQD Send Signal via Time Queue Double

a Format:

XSTQD r;

b Function:

A signal is entered in a central time queue for a specied time delay. Theaddress to which the signal is sent can either be its own block or anotherblock. Each transferred data is 32 bits.

There are four time queues, TQA, TQB, TQC and TQC. TQA is an absolutetime queues, the others are relative. The characteristics are:

c TQA

The month is specied with the gures 0-12. The day is specied with thegures 0-31. If 0 is specied for the month, the signal is delayed until thespecied day, hour and minute occurs. The corresponding procedure isadopted if the day = 0.

d TQB

100 ms long time intervals.

8/12/2019 Asa Manual 2006







e TQC


f TQD


Input data for the instruction is fetched from register r and subsequentregisters.

TQA15 12 11 9 8 4 3 1 2 0

stype=0 bn-r r

ssp f r+1

0 tq jb r+2

month day r+3

hour minute r+4

TQB, TQC, TQD15 12 11 9 8 4 3 1 2 0

stype=0 bn-r r

ssp f r+1

0 tq jb r+2

number of time intervals r+3

a

When XRST is used in macro the following applies:bn-r is zero for uniquesignals.bn-r is not equal to zero for multiple signals.

ssp is the position in the signal sending table in the block for the signalto be sent.

b Note 1:


c Note 2:

8/12/2019 Asa Manual 2006







Registers r, r+1 and r+2 can be loaded with the aid of macros TQINF orTQINFI.

d Note 3:

The delay in the relative time queues will be at least the nominal time. Themaximum delay is the nominal time plus the ’delay unit’ of the time queue.E.g. a nominal delay of 5 seconds in TQC will in reality be between 5and 6 seconds.

8.17 SSRP, Send Signal to RP

a Format:

SSRP var, f, c, r;

b Function:

This instruction is used for transmitting signals from central to regionaldevice programs included in the same function block.

A signal number is specied in process register r. Pointer register PR0contains the relevant device pointer. Variable var is the distributed RP-tablewhich contains the RP-address and CM-address.

If E-bit=1 in distributed RP-table, the RP-table has a second word whichcontains CME (E=1 indicates signal to EMG).

The number of devices per CM is specied by 2exp(c), i.e. c shall have thevalue 2log(number of devices per CM).

Data accompanies the signal according to format f. The data is fetchedfrom the DR-registers and a maximum of 12 data words with a maximumof 8 bits each may be transmitted.

c Example:

SSRP RPTAB, 4, 2, AR0;

A signal with the number specied in AR0 is sent to a device programin RP. The internal address within the RP and the RP-number will becalculated from the contents of PR0 and the distributed RP-table RPTAB.Pointer and four 8-bit data will be sent. There are four devices on each CM.

15 11 10 9 8 7 0

cm-addr B E RP address

CME

8/12/2019 Asa Manual 2006







a

B indicates if the CM/RP is blocked. ’var’ is addressed with bit c-15of PR0as a pointer. (c = parameter c).

b Note 1:

If the RP is blocked, the operating system will take over control.

c Implementation:

The assembler instruction SSRP generates one of the machine operationsSSRPU or SSRPL. SSRPU will be generated if the base address of var is1-255, else SSRPL will be generated.

8.18 SSRPE Send Signal TO RP Extended

a Format:

SSRPE var, f, c, r;

b Function:

This instruction is used for transmitting signals from central to regionaldevice programs included in the same function block.

A signal number is specied in process register r. Pointer register PR0contains the relevant device pointer. Variable var is the distributed RP-tablewhich contains the RP-address and CM-address.

If E-bit=1 in distributed RP-table, the RP-table has a second word whichcontains CME (E=1 indicates signal to EMG).

The number of devices per CM is specied by 2exp(c), i.e. c shall have thevalue 2log(number of devices per CM).

Data accompanies the signal according to format f. The data is fetchedfrom the DR-registers and a maximum of 48 data words with a maximum of8 bits each may be transmitted. The data are fetched from DR-registerswith two bytes in each register. The rst data is in DR0/H0, the second inDR0/H1, the third in DR1/H0 and so forth.

c Example:

SSRPE RPTAB,10,2,AR0;

A signal with the number specied in AR0 is sent to a device programin RP. The internal address within the RP and the RP-number will becalculated from the contents of PR0 and the distributed RP-table RPTAB.Pointer and 32, 8-bit data will be sent. There are four devices on each CM.

8/12/2019 Asa Manual 2006







15 11 10 9 8 7 0

cm-addr B E RP address

CME

a

B indicates if the CM/RP is blocked. ’var’ is addressed with PR0/2exp(c) asa pointer. (c = parameter c).

b Note 1:

If the RP is blocked, the operating system will take over control.

c Note 2:

All RP:s can not handle ’long’ RP signals.

d Implementation:

The assembler instruction SSRPE generates one of the machineoperations SSRPEU or SSRPEL. SSRPEU will be generated if the baseaddress of var is 1-255, else SSRPEL will be generated.

8.19 SSIP, Send Signal to IPNA

a Format:

SSIP var, f, r;

b Function:

This instruction is used for transmitting signals from central software tosoftware on IPNA included in the same function block.

The destination (Logical IPNA Address plus IPNASUP) of the signal isspecied by the variable ’var’ (the content of which is provided by the ’O&Mowner of IPNA’).

Pointer register PR0 is used for addressing of variable ’var’.

The signal number is specied by register ’r’. The register also speciestype and priority of the signal.

If the type states that a CB/DB is included in the signal, the registers’r+1’-’r+4’ will specify the buffer. Data in the buffer are packed bytes,meaning that the data length of the variables in the buffer is 8 bits (byte)and two bytes are packed in a 16 bits word. Both, start index and numberof data can be odd or even.

8/12/2019 Asa Manual 2006







Data according to format f will be sent with the signal. If a CB/DB isincluded in the data, rst signal (including the buffer description in’r+1’-’r+4’) will be sent to IPNA, then the CB/DB will be sent with ’softDMAsignals’ to IPNA. 16 bits of data is transferred from each DR register.

Note:

After a block has sent one signal with CB/DB to IPNA, the same blockcannot send the next signal with CB/DB to IPNA on the same priority leveluntil the rst one has been acknowledged. For signals without CB/DBthere are no such restriction. Different CP blocks can simultaneously sendsignals with CB/DB to the same IPNA.

Data Structure:

Variable 'var'

15 8 7 1 0

IPNASUP Logical IPNA address

Logical IPNA address = Bit 0 Subaddress (A/B side)Bit 7-1 Logical IPNA number

IPNASUP = IPNA Software Unit PointerLogical IPNA number = (31 - Logical RPHB address)

Registers r, r+1, ..., r+4:

15 14 11 8 7 0

r P Type Signal Number

r+1 Number of buffered data / Data

r+2 Buffer pointer LSW / Data

r+3 Buffer pointer MSW / Data

r+4 Start index in buffer / Data

Type = 0 - No DB/CB included1 - DB/CB included

P(Priority) = 0 - Normal1 - High

8/12/2019 Asa Manual 2006







8.20 SSIPD, Send Signal to IPNA Double

a Format:

SSIPD var, f, r;

b Function:

This instruction is used for transmitting signals from central software tosoftware on IPNA included in the same function block.

The destination (Logical IPNA Address plus IPNASUP) of the signal isspecied by the variable ’var’ (the content of which is provided by the ’O&Mowner of IPNA’).

Pointer register PR0 is used for addressing of variable ’var’.

The signal number is specied by register ’r’. The register also speciestype and priority of the signal.

If the type states that a CB/DB is included in the signal, the registers’r+1’-’r+4’ will specify the buffer. Data in the buffer are packed bytes,meaning that the data length of the variables in the buffer is 8 bits (byte)and two bytes are packed in a 16 bits word. Both, start index and numberof data can be odd or even.

Data according to format f will be sent with the signal. If a CB/DB isincluded in the data, rst signal (including the buffer description in’r+1’-’r+4’) will be sent to IPNA, then the CB/DB will be sent with ’softDMAsignals’ to IPNA. 32 bits of data is transferred from each DR register.

Note:

After a block has sent one signal with CB/DB to IPNA, the same blockcannot send the next signal with CB/DB to IPNA on the same priority leveluntil the rst one has been acknowledged. For signals without CB/DBthere are no such restriction. Different CP blocks can simultaneously sendsignals with CB/DB to the same IPNA.

Data Structure:

8/12/2019 Asa Manual 2006







Variable 'var'

15 8 7 1 0

IPNASUP Logical IPNA address

Logical IPNA address = Bit 0 Subaddress (A/B side)Bit 7-1 Logical IPNA number

IPNASUP = IPNA Software Unit PointerLogical IPNA number = (31 - Logical RPHB address)

Registers r, r+1, ..., r+4:

15 14 11 8 7 0

r P Type Signal Number

r+1 Number of buffered data / Data

r+2 Buffer pointer LSW / Data

r+3 Buffer pointer MSW / Data

r+4 Start index in buffer / Data

Type = 0 - No DB/CB included1 - DB/CB included

P(Priority) = 0 - Normal1 - High

8.21 XRST, Read from Signal Sending Table

a Format:

XRST r-sig,b;

b Function:

Transfer of signal sending pointer (ssp) or block number from the GlobalSending Distribution Table (GSDT-U) to processor register.If b=0 r isloaded with ssp.If b=1 and the signal type is unique r is loaded with BN-R,otherwise zero is loaded.

The instruction forms the input data in register r and r+1 to XSTQ (XSTQD)and the instruction is normally included in the macro TQINF (TQINFI).

c Example:

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







c Example:

RECEIVE BULKSIG;RBD 5, WR9;

The signal BULKSIG is received with ordinary signal data registers andbulk data. The pointer to the Communication Buffer where the bulk data isstored is found in the register WR9.The size of the Communication Buffer is 512 W16.

d Implementation:

This instruction is only available on APZ 212 40 and later.

e Note:

It is not recommended to use this instruction in a correction.

8.23 SSRPB, Send Bulk Signal to RP

a Format:

SSRPB var, f, c, b, r;

b Function:

This instruction is used for transmitting signals from central to regionaldevice programs included in the same function block using the RPB-E bus.

A signal number is specied in process register r.The Pointer register PR0 contains the relevant device pointer.Variable var is the distributed RP-table, which contains the RP-addressand CM-address.

The register r+1 species the pointer to the Communication Buffer whichcontent will be (fully/partly) transferred to the RP.

The compare register CR contains the number of W16 words that mustbe sent.If the b-bit is set to one only the least signicant W8 of each word of theCommunication Buffer is sent, else if b-bit is zero W16 of each word ofthe Communication Buffer is sent.

If CR is zero no bulk data will be sent in the signal. If CR is non-zeroand r+1 does not contain a valid Communication Buffer (r+1=0) aPROGERROR occurs.

The index register IR contains the index to the rst W16 of theCommunication Buffer to be sent.

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







9 Miscellaneous Instructions

9.1 EP, End of Program

a Format:

EP;

b Function:

The EP is used at the following events:

- local linked return

- combined backward signal

- concluding of a job on TRL, THL1, THL2, THL3, BAL1 or BAL2 level.

c Implementation:

The function of the EP-instruction, is controlled by the contents of the topposition of the link register stack (LR):

- if BN of LR is equal to the block number of current block a local linkedreturn is performed or a combined backward signal within the block is sent.The program execution will then continue in this block at address accordingto IA value from LR.

- if BN of LR differs from the block number of current block and is not equalto zero, a combined backward signal is sent to this other block. This meansthat the program execution will continue at address according IA valuefrom LR in the new block.

- If BN of LR is equal to zero the current job will be concluded. Thecontinued execution is then controlled in the following way:

-- If the concluded job was a TRL-job, a return to the interrupted level withhighest priority is executed

-- If the concluded job was a job table job (THL1), the job table search willcontinue if the whole job table has not been searched.

If the search is nished a job on THL2 or THL3 is started if there is anywaiting, else a return to interrupted job on BAL is executed.

-- If the concluded job was a THL2 or a THL3 job, a new THL job is startedif there is any waiting, else a return to interrupted job on BAL is executed.

-- was the concluded job a BAL1 or a BAL2 job, a new BAL job is started ifthere is any waiting.

d Note:

8/12/2019 Asa Manual 2006







When a return to interrupted job is to be performed but there is nointerrupted job or when a BAL job is concluded without any new BAL job tostart, then an idle-loop is entered.

9.2 SRT , Set Return Time

a Format:

SRT w;

b Function:

A time is set in the job table. This instruction is used in programs whichare called from a job table. The instruction sets the counter word of the jobtable = w. If parameter w = 0, the value is fetched from IR.

c Example:

SRT 496;

The program is called from the job table after 496 primary intervals, i.e.4960 ms.

d Note:

SRT must be executed in each job table job before it is ended withinstruction EP. If not, software recovery actions are taken.

10 Search Instructions

10.1 BLO, Bit search for Leftmost One in Register

a Format:

BLO r, c, l;

b Function:

A search for a bit set to one from left to right in process register r. Thesearch starts at the bit position specied by character constant c andcontinues with the next lower signicant bit position. The search isconcluded when a bit set to one is encountered or when bit position 0 hasbeen searched. If c = 0, index register IR character 0 indicates wherethe search is to begin.

If a bit set to one is encountered, it is cleared to zero and a bit address isstored right-justied in index register IR. IR is cleared to zero before thestorage operation is carried out. A jump is then done to program label l.

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







c Example:

CS STR1, WR9, STR2, WR10;

The two string variables STR1 and STR2 will be compared. If the arestored in a RECORD then WR9 indicates the actual pointer value forSTR1 and WR10 indicates the pointer value for STR2. The result of thecomparison is found in the CR register.

d Note:

The comparison between var1 and var2 will be strictly numerical and themicro program will not perform any check whether the compared 8-bitnumbers are valid ASCII characters.

10.4 FESR, File search for Equality between Store and Register

a Format:

FESR var, l;

b Function:

To search for similarity between variables and the contents of comparison

register CR. The variables belong to the variable block var and have to beaddressed by pointer.

The search starts with the variable specied by the start pointer value inprocess register PR0 reduced by 1. The search continues with the nextvariables with lower pointer values, where upon PR0 is decremented.

If the search condition is met, the relevant pointer value is stored in PR0and a jump takes place to program label l.

When the variable which is indicated by PR1 has been scanned withoutmeeting the search condition, the search is concluded and PRO is set equalto PR1. The program then continues with the next instruction in sequence.

If PR0 is less than or equal to PR1 from the beginning, the programcontinues with the next instruction in sequence with unchanged pointervalues.

c Example:

FESR FAELT, INIT;

A variable with a value specied in comparison register CR is sought invariable block FAELT. If the value is found, a jump takes place to programlabel INIT.

d Note 1:

8/12/2019 Asa Manual 2006







The instruction cannot be used for variables larger than 32 bits or forsubvariables or indexed variables.

e Note 2:

The instruction can be interrupted. This means that the instructioncan be temporarily concluded if, for example, a maintenance interruptsignal arrives during the execution of the instruction. When the interruptsequence has been concluded, the execution of the instruction continues.

f Implementation:

The assembler instruction FESR generates one of the machine operationsFESRU or FESRL. FESRU will be generated if the base address of var is1-255, else FESRL will be generated.

10.5 FCZS, File search for Change to Zero in Store

a Format:

FCZS var, l;

b Function:

An array of counters in the data store is run through and each counteris decremented by 1. When a counter reaches zero, an exit takes placeto label l. Counters whose initial value are zero will not be decrementedand in this case the run through shall continue with the next counterunconditionally. Each counter is contained in a variable, addressed by apointer, in variable block var.

The search begins with the variable specied by the start pointer value inprocess register PR0 reduced by 1. The search continues with the nextvariables with lower pointer values, where upon PR0 is decremented.

If the search condition is met, the relevant pointer value is stored in PR0and a jump takes place to program label l.

When the variable which is indicated by PR1 has been searched withoutthe search condition having been met, the search is concluded and PR0is set equal to PR1. The program then continues with the next instructionin sequence.

If PR0 is less than or equal to PR1 from the beginning, the programcontinues with the next instruction in sequence with unchanged pointervalues.

c Example:

FCZS IDLE, FOUND;

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







The address to program label START will be included in the sequence ofinstructions when loading the program unit to the program store.

d Code generation:

16-bit binary value

11.2 BLNR, Load Block Reference Number

a Format:

BLNR r-blnm;b IMPORTANT:

MUST NOT BE USED IN ASSEMBLER PROGRAMS

c Function:

Reference of own block is loaded in register r. The reference is composedfrom own block number according to the gure.

15 8 3 0

bn bit 0-7 0 b: 8-11

a Note:

APS does not use the ’blnm’ parameter. Own (current) block number isalways used.

b Example:

BLNR WR2-RC;

If own block number is H’394 WR2 will contain the value H’9403 when

BLNR is executed, whether own block is RC or not.

c Code generation:

XRBN r;ROL r, 8;

11.3 DUPL, Duplicate Instruction

a Format:

DUPL w;

b Function:

8/12/2019 Asa Manual 2006







The next instruction in sequence is repeated w times.

c Note:

If the instruction after DUPL is a macro instruction, only the last instructionin the macro’s code generation is repeated.

d Example:

DUPL 3;XSTP H’10FF;

The generated assembler instructions will be follows:

XSTP H’10FF;

XSTP H’10FF;

XSTP H’10FF;

11.4 ERD, Exclusive or in Register

a Format:

ERD r1-r2;

Exclusive ’OR’ is done between the contents of process registers r1 and r2and the result is stored in r1.

b Example:

ERD AR1-AR2;

An exclusive ’OR’ is done between the contents of process registers AR1and AR2. The result is stored in AR1.

c Code generation:

ER r1, r2;

11.5 JECD, Jump on Eq with Char Constant Double

a Format:

JECD r, c, l;

b Function:

If the contents of process register r are equal to program constant c, a jump is done to a program label l.

c Example:

8/12/2019 Asa Manual 2006







JECD WR1, 6, TEST;

A jump is done to program label TEST if process register WR1 containsthe number 6.

d Code generation:

JEC r, c, l;

11.6 JERD, Jump on Equality between Register Double

a Format:

JERD r, l;

b Function:

If process registers r and CR contain equal values, a jump is done to aprogram label l.

c Example:

JERD WR4, EQ; The jump is done to program label EQ is the contents ofprocess registers WR4 and CR are equal.

d Code generation:

JER r, l;

11.7 JGETD Jump on Greater Than or Equal Double

a Format:

JGETD r, l;

b Function:

If the value in process register r is greater than or equal to the value inprocess register CR, a jump is done to a program label l.

c Example:

JGETD WR5, END;

A jump is done to program label END if the contents of process registerWR5 are greater than or equal to the contents of CR.

d Code generation:

JGET r, l;

8/12/2019 Asa Manual 2006







11.8 JGTD, Jump on Greater Than Double

a Format:

JGTD r, l;

b Function:

If the value of process register r is greater than the value of processregister CR, a jump is made to a program label l.

c Example:

JGTD WR0, BEGIN;

A jump is done to program label BEGIN if the contents of process registerWR0 are greater than the contents of CR.

d Code generation:

JGT r, l;

11.9 JLETD Jump on Less Than or Equal Double

a Format:

JLETD r, l;

b Function:

If the value in process register r is less than or equal to the value in processregister CR, a jump is done to a program label l.

c Example:

JLETD WR0, PASS;

A jump is done to program label PASS if the contents of process register

WR0 are less than or equal to the contents of CR.

d Code generation:

JLET r, l;

11.10 JLTD, Jump on Less Than Double

a Format:

JLTD r, l;

b Function:

8/12/2019 Asa Manual 2006







If the value of process register r is less than the value of process registerCR, a jump is made to a program label l.

c Example:

JLTD WR9, ROUTINE;

A jump is done to program label ROUTINE if the contents of processregister WR9 are less than the contents of process register CR.

d Code generation:

JLT r, l;

11.11 JUCD, Jump on Unequality with Char Const Double

a Format:

JUCD r, c, l;

b Function:

If the contents of process register r and program constant c have differentvalues, a jump is done to a program label l.

c Example:

JUCD WR3, 12, OUT;

A jump is done to program label OUT if process register WR3 containsany value other than the number 12.

d Code generation:

JUC r, c, l;

11.12 JURD, Jump on Unequality between Register Double

a Format:

JURD r, l;

b Function:

If the contents of process register r and CR are unequal, a jump is doneto a program label l.

c Example:

JURD WR0, UQ;

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







b Function:

Character constant c is transferred to a variable in process register r. Thelength and position of the variable within the register are specied by vlm.

c Code generation:

LHCE r/vlm-h;

11.16 LWC, Load Word Constant

a Format:

LWC r-w;

b Function:

Word constant w is transferred to process register r.

c Example:

LWC WR6-1025;

Numeric value 1025 is stored in process register WR6.

d Code generation:

LHC r/W0-’w/b0-7’;LHC r/H1-’w/b8-15’;

11.17 NHC, Logical aNd with Halfword Constant

a Format:

NHC r-h;

b Function:

A logical ’AND’ is carried out between program constant h and the contentsof process register r. The result is stored in the process register.32 bitsare affected.

Each bit in r is changed in accordance with the following truth table:

r

0 1

h 0 0 0

1 0 1

8/12/2019 Asa Manual 2006







a

Result indicator RIR is cleared if the result is zero and is set to one if theresult is not zero.

b Example:

NHC AR3-H’D4;

Logical ’AND’ is carried out between hexadecimal number 00D4 and thecontents of process register AR3.

c Code generation:

NWC r-w;

11.18 RECEIVE, Receive a Signal

a Format:

RECEIVE sig;

b Function:

The label for receiving a signal is specied with the aid of RECEIVE.

c Example:

RECEIVE SEIZE;

The location of the statement species the relevant address for receivingsignal SEIZE.

d Code generation:

No code, only a denition of the entry label.

11.19 SGLOC Signal Group Location

a Format:

SGLOC r-sgn;

b Function:

Process register r is allocated a signal group position in own blocks signaldistribution table. sgn species the signal group name.

c Code generation:

LHC r/W0-’signal group pos bit 0-7’LHC r/H1-’signal group pos bit 8-11’

8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







n species the instruction address to the program label to which the jumpis to take place.

11.22 TQINF Time Queue Information

a Format:

TQINF r-sig, tq;

b Function:

Allocation of block number in register r, signal number and format inregister r+1 and time queue index and job buffer index in register r+2.Signal sending pointer (ssp), data format (f) and job buffer index (jb) arespecied by sig. With the aid of ssp block number and signal number areread from the signal sending table of current block.

The values received can, together with programmed settings of subsequentregisters (see note 1) be used by any of the instructions XSTQ or XSTQD(insertion of signal message in central time queue).

Registers r, r+1 and r+2 are allocated values in accordance with thefollowing:

15 0

stype=0 bn-r r

sn f r

0 tq jb r+2

a Note 1:

The subsequent registers, register r+3 and, where applicable, register r+4shall also be set before the instruction XSTQ can be executed. In the caseof time queue TQA, the month and day are allocated in register r+3 in theleft-hand and right-hand half-words respectively. The hour and minuteare allocated in register r+4 in the left-hand and right-hand half-wordsrespectively.

In the case of time queues TQB, TQC and TQD, a delay is specied as amultiple of 100 ms, 1 second and 1 minute respectively in register r+3.

b Note 2:


8/12/2019 Asa Manual 2006


8/12/2019 Asa Manual 2006







VAL w;

b Function:

Numeric value w will be generated in binary form and with a eld lengthof 16 bits. Instruction VAL is used for writing machine instructions in puremachine code and for organizing tables in the program store.

c Example:

VAL H’384B;

The hexadecimal value 384B will be included in the sequence of machineoperations.

d Code generation:

16-bit binary code

11.25 XLLR, Load Location in Register

a Format:

XLLR r-l;

b Function:

The address to program label l within the same program unit is transferredto process register r.

c Example:

XLLR WR4-TESTLCC;

The relative address for TESTLCC is stored in register WR4.

d Code generation:

LHC r/W0 ’address/B0 7’;LHC r/H1 ’address/B8 13’;

Asa Manual 2006

Documents

Transcript of Asa Manual 2006