M3 Proceso CMOS

7/27/2019 M3 Proceso CMOS

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PROCESO CMOSVanessa Vargas

Quito, Septiembre 2010

ESCUELA POLITCNICA DEL EJRCITO

DISEO VLSI


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DISEO VLSI

Introduction

Recurring steps Process FlowManufacturing

Design Rules

Layer Representation

Conclusion

CMOS PROCESS


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INTRODUCTION

INTRODUCCIN

No debe saber detalles del proceso.Pero debe tener conocimientos generales de constraints fsicas,costos, etc.

DigitalDesigner

Define los patterns(patrones) apli cados a los diferentes layers(capas)del semiconductor.

Interface:Optical Masks

Conjunto de constraints(restriccin)Ancho y separacin mnima entre patternsContrato entre circuit designer y process engineerGaranta de que el circuito sea realizable con xitoDesign Rules


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INTRODUCTION

WELL ANS SUBSTRATES


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INTRODUCTION

MODERN DUAL WELL PROCESS

p-well n-well

p+

p-epi

SiO2

AlCu

poly

n+

SiO2

p+

gate-oxide

Tungsten

TiSi2

Dual-Well Trench-Isolated CMOS Process


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MANUFACTURING

PHOTOLITOGRAPHYSi-substrate

Si-substrate

(a) Silicon base material

(b) After oxidation and depositionof negative photoresist

(c) Stepper exposure

Photoresist

SiO2

UV-light

Patternedoptical mask

Exposed resist

Si-substrate

Opcional SiO2 aplicable para

aislar(insulate) gate

OxidationLayering

Light sensitive polimer(latex) Aplicado mientras gira el wafer Espesor 1 um Original soluble Insoluble al exponer a UV

Photoresistcoating

Glass mark over the wafer Contains patterns Mask+ wafer exposed to UV

Stepperexposure


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MANUFACTURING

PHOTOLITOGRAPHY

Remueve non-exposed areas concido o base

Luego es horneado paraendurecer el photoresist

permanente

Photoresistdevelopme

nt

Material removido de reas sinphotoresist

Varios qumicos peligrosos sonusados

Etching

SPIN+Rinse+Dry Wafer limpiado con agua Secado con nitrgeno

SRD

SiO2

Si-substrate

Si-substrate

SiO2

(d) After development and etching of resist,chemical or plasma etch of SiO

2

(e) After etching

Hardened resist

Hardened resist

Chemical or plasmaetch


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MANUFACTURING

PHOTOLITOGRAPHY

2 mtodos para introducir implantes rea expuesta es dopada, el resto es cubierta de

material buffer SiO2

Diffusion andIon implantation

Wafers colocados dentro de tubo de cuarzo enhorno

Gas con dopantes introducido en tubo.Calentamiento 900-1000 C

Concentracin final decrece desde la superficie.

Diffusion

Dopantes introducidos mediante un haz de iones Permite control de profundidad y dosis(aceleracin,

corriente y tiempo) Mtodo ha superado a la difusin Drawback: lattice damage. Corregido con

annealing. Wafer calentado, vibracin arreglaestructura de tomos.

Ion

Si-substrate

SiO2

(f) Final result after removal of resist


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MANUFACTURING

PHOTOLITOGRAPHY

Colocar layers de material sobre el wafer Material: buffer, insulating, conducting Diferentes mtodos para cada caso. Ejm. SiO2,

aluminio, etc

Deposition

Formar patterns selectivamentes(wires, contacts) Tradicionalmente se ha usado cido o base. Actualmente: plasma(nitrogen, chorine, baron

thricloride)

Etching

Obtener superficie plana Es importante previo deposition CMP Method(Chemical-mechanical planarization).

Lquido con material abrasivo( xido de aluminio oslica)

Planarization


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MANUFACTURING

CMOS PROCESSoxidation

opticalmask

processstep

photoresist coatingphotoresistremoval (ashing)

spin, rinse, dryacid etch

photoresist

stepper exposure

development

Typical operations in a singlephotolithographic cycle (from [Fullman]).


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PROCESS FLOW

Define active areasEtch and fill trenches

Implant well regions

Deposit and patternpolysilicon layer

Implant source and drainregions and substrate contacts

Create contact and via windowsDeposit and pattern metal layers

Source: Digital Integrated CircuitsA Design Perspective

Jan M. RabaeyAnantha Chandrakasan

Borivoje Nikolic


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PROCESS FLOW

p+

p-epi (a) Base material: p+ substratewith p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse ofthe active area mask

p+

p-epiSiO2

3SiN4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)


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PROCESS FLOW

SiO2

(d) After trench filling, CMPplanarization, and removal ofsacrificial nitride

(e) After n-well andVTp adjust implants

n

(f) After p-well andVTn adjust implants

p


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PROCESS FLOW

(g) Afterpolysilicon depositionand etch

poly(silicon)

(h) After n+source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2


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PROCESS FLOW

(j) After deposition andpatterning of first Al layer.

Al

(k) After deposition of SiO2

insulator, etching of vias,deposition and patterning ofsecond layer of Al.

AlSiO

2


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PROCESS FLOW

INTERCONNECT IMPACT ON A CHIP


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PROCESS FLOW

ADVANCED METALLIZATION


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DESIGN RULES

entre el ingeniero diseador y elingeniero de procesos

Se requiere de unInterfaz

Guas deconstruccin para lasmscaras de proceso

Reglas de diseo escalables:parmetro lambda

Dimensiones absolutas (reglas micron )

Dimensin de launidad: el ancho de

lnea mnimo


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DESIGN RULES

INTRA LAYER

10

90

Well

Active3

3

Polysilicon

2

2

Different PotentialSame Potential

Metal13

3

2

Contactor Via

Select

2

or6

2Hole


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DESIGN RULES

VIAS AND CONTACTS

1

2

1

Via

Metal toPoly ContactMetal to

Active Contact

1

2

5

4

3 2

2


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DESIGN RULES

INTER LAYER


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LAYER REPRESENTATION

EJM. COLOR REPRESENTATIONLayer

Polysilicon

Metal1

Metal2

Contact To Poly

Contact To Diffusion

Via

Well (p,n)

Active Area (n+,p+)

Color Representation

Yellow

Green

Red

Blue

Magenta

Black

Black

Black

Select (p+,n+) Green


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CMOS INVERTER LAYOUT

A A

np-substrate Field

Oxidep+n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A

A A


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CMOS LAYOUT EDITOR

M3 Proceso CMOS

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