VHDL State Machines 1
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Synchronous sequential design Msc Heiner Castro G.
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Transcript of VHDL State Machines 1
8/6/2019 VHDL State Machines 1
http://slidepdf.com/reader/full/vhdl-state-machines-1 1/14
Synchronous sequentialdesign
Msc Heiner Castro G.
8/6/2019 VHDL State Machines 1
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Synchronous sequential
systemsLa mayoría de lossistemas digitalesmodernos sonsecuenciales ysíncronos.
Los sistemas más
complejos no puedenrepresentarse en sutotalidad como eldiagrama, pero por lo
menos una parte si –
launidad de control-
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Moore Machine
En una Moore machine la salida solo depende delestado presente del sistema.
Los bloques para calcular el siguiente estado y la
salida son combinacionales.
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Mealy Machine
En una Mealy machine la salida no solodepende del estado presente si no de las
entradas en ese instante.
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State Machine Example
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State Machine Example
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State Machine Example: ASM charts(Algorithmic State Machines)
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ASM Charts: state and mealyoutputs differences
z
c
Y
w
1
0
a)
z
c
w
1
0
b)
Y
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Entity of the state machine:Traffic Light
library IEEE;
use IEEE.std_logic_1164.all;entity traffic is
port (clock, reset, timed, car : in std_logic;start_timer, major_green, minor_green : out std_logic);
end entity traffic;
8/6/2019 VHDL State Machines 1
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Architecture of the state machineTraffic Light: 1 process
architecture asm1 of traffic is
begin
process (clock) is
type state_type is (G, R); variable state : state_type;
begin
start_timer <= '0';
if (rising_edge(clock)) then
case state is
when R =>
major_green <= '0';
minor_green <= '1';
if (timed = '1') then
when G =>
major_green <= '1';minor_green <= '0';
if (car = '1') then
start_timer <= '1';
state := R;
end if ;
end case;
end if ;
end process;
end architecture asm1
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Architecture of the state machine:Traffic Light: 2 Processes
architecture asm2 of traffic is
type state_type is (G, R);
signal present_state, next_state:
state_type;
begin
seq: process (clock, reset) is
begin
if (reset = '1') then
present_state <= G;
elsif (rising_edge(clock)) then
present_state <= next_state;
end if ;
end process seq;
com: process (car, timed, present_state) is
begin
case present_state is
when G =>
major_green <= '1';
if (car = '1') then
start_timer <= '1';
next_state <= R;
else
next_state <= G;
end if ;
when R =>minor_green <= '1';
if (timed = '1') then
next_state <= G;
else
next_state <= R; end if
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Architecture of the state machine:Traffic Light: 3 Processes
architecture asm3 of traffic is
type state_type is (G, R);signal present_state,
next_state : state_type;begin
seq: process (clock) is
begin
if (rising_edge(clock))
thenpresent_state <=
next_state;
end if ;
end process seq;
ns: process (car, timed,
case present_state is
when G =>
if (car = '1') then
next_state <= R;
else
next_state <= G;
end if ;
when R =>
if (timed = '1') then
next_state <= G;
else
next_state <= R;
end if ;
end case;
op: process (car,present_state) is
begin
start_timer <= '0';if (present_state = G) then
major_green <= '1';
minor_green <= '0';
if (car = '1') then
start_timer <= '1';end if ;
else
major_green <= '0';
minor_green <= '1';
end if ;end process op;
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Arch. of the state machine TrafficLight: 2 Processes + Comb Block
architecture asm3a of traffic is
type state_type is (G, R);
signal present_state, next_state :
state_type;begin
seq: process (clock) is
begin
if (rising_edge(clock)) then
present_state <=next_state;
end if ;
end process seq;
ns: process (car, timed,present_state) is
--Combinational block start_timer <= '1' when (present_state = G and car = '1'
else '0';
major_green <= '1' when (present_state = G) else '0';
minor_green <= '1' when (present_state = R) else '0';
end architecture asm3a;
case present_state is
when G =>
if (car = '1') then
next_state <= R; else next_state <= G;
end if ;
when R =>
if (timed = '1') then
next_state <= G; else next_state <= R;
end if ;
end case;
end process ns;
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State machine exercise
Diseñar usando un diagrama ASM el doble semáforo de un crucede calle. Las señal solo debe cambiar cuando un automóvil esdetectado en una dirección con luz roja. En una semaforizaciónnormal las luces cambian así: Rojo-Rojo_Ambar-Verde-Ambar-
Rojo. Note que cuando las luces en una dirección es verde, ambaro rojo-ambar la luz en la otra dirección debe ser rojo (entonces senecesitan más de 4 estados).
Los tiempos serán de esta forma:
Rojo: 20s
Rojo_Ambar: 5s
Verde: 20s
Ambar: 5s
Los temporizadores debe declararlos como componentes ysuponer que ya están descritos. Típicamente un temporizadortiene 3 entradas: clk, reset y start que inicia la temporización.
