Vedics Details

8/12/2019 Vedics Details

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Vedic Mathematics i s t he n ame given to the a ncient system of IndianMathematics w hich was r ediscovered from the Vedas b etween 1911 and 1918by S ri Bharati Krsna Tirthaji (1884-1960). According to his r esearch all ofmathematics i s b ased on s ixteen Sutras, or word-formulae. For example,'Vertically and Crosswise is one of these Sutras. These formulae describe theway the mind naturally works and are therefore a great help in directing thestudent to the appropriate method of solution.

This u nifying quality is v ery s atisfying, it makes m athematics easy andenjoyable and encourages i nnovation.

Vedic mathematics sutras (principles) 16

1. By one more than the one before.2. All from 9 and the last from 103. Vertically and Cross-wise4. Transpose and Apply5. If the Sam ccaya is the same it is !ero6. If one is in "atio the other is #ero7. By addition and by S bstraction8. By the completion or $on-completion9. %i&erential Calc l s.10. By the %e'ciency11. Speci'c and (eneral12. The remainders by the last di)it13. The ltimate and Twice the *en ltimate14. By one less than the one before15. The prod ct of the s m16. All the m ltipliers.


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The system is based on 16 sutras or aphorisms, such as: "by one more than the onebefore" and "all from nine and the last from 10". These describe natural processes in themind and ways of solving a whole range of mathematical problems. For e ample, if wewished to subtract !6 from 1,000 we simply apply the sutra "all from nine and the lastfrom 10". #ach figure in !6 is subtracted from nine and the last figure is subtracted

from 10, yielding $6.

The sutra "vertically and crosswise" has many uses. %ne very useful application ishelping children who are having trouble with their tables above ! !. For e ample & '. &is $ below the base of 10, and ' is ( below the base of 10.

The sutra "vertically and crosswise" is often used in long multiplication. )uppose wewish to multiply$( by . *e multiply vertically ( +'.Then we multiply crosswise and add the two results: $ (+(0, so put down 0 andcarry (.Finally we multiply vertically $ +1( and add the carried ( +1 . -esult: 1, 0'.


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Books:

#/ 23T4#23T )%r )i teen )imple 2athematical Formulae from the edas The original introduction to

edic 2athematics. 3uthor: 5agadguru )wami )ri harati 7rsna Tirtha8i 2ahara8a,196! various reprints;.e.

) ? '1 (0' 016$ 6 cloth;) ? '( (0' 016$ paper;@p

23T4) %- 23A BThis is a popular boo= giving a brief outline of some of the edic 2athematics methods.

3uthor: 5oseph 4owse. 19&6) ? 0&(( 01 $urrently out of print.@p

#/ 23T4#23T )2aster 2ultiplication tables, division and lots moreC

*e recommed you chec= out this eboo=, itDs pac=ed with tips,tric=s and tutorials that will boost your math ability, guaranteedC www.vedicEmathsEeboo=.com

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?T-%/ T%-G H# T -#) %? #/ 23T4#23T )Following various lecture courses in Hondon an interest arose for printed materialcontaining the course material. This boo= of 1( chapters was the result covering arange topics from elementary arithmetic to cubic eIuations.

3uthors: 3.


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# ercise 1 Tutorial

Try these:

1) ! ( +

2) 6! ( +

3) 9! ( +

4) $! ( +

/oes divide evenly into 1($ B

For 4 to divide into an n!"#er $e %aveto "a&e '!re t%at t%e (a't n!"#er i' even

f it is an odd number, there is no way it will go in evenly.)o, for e ample, will not go evenly into 1($$ or 1($!

?ow we =now that for to divide evenly into anynumber the number has to end with an even number.

ac= to the Iuestion...

into 1($ , the solution:

Ta&e t%e (a't n!"#er and add it to 2 ti"e' t%e 'e ond (a't n!"#er f goes evenly into this number then you =now

that will go evenly into the whole number.

)o ( K $; + 10 goes into 10 two times with a remainder of ( so it does not go in evenly.

Therefore into 1($ does not go in completely.

HetLs try into $ $6! 6

)o, from our e ample, ta=e the last number, 6 and add it totwo times the penultimate number,

6 ( K ; + 1 goes into 1 three times with two remainder.

)o it doesnDt go in evenly.


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HetDs try one more.

into (1($$ $6

6 ( K $; + 1(

goes into 1( three times with 0 remainder.

Therefore goes into ($ $6 evenly.

Vedic Mathematics is a super fast way ofcalculation whereby you can dosupposedly complex calculations like 998

x 997 in less than ve seconds at! "t ishi#hly bene cial for school and colle#estudents and students who are appearin#for their entrance examinations!

Vedic Mathematics is far moresystematic$ simpli ed and uni ed than

the conventional system! "t is a mentaltool for calculation that encoura#es thedevelopment and use of intuition andinnovation$ while #ivin# the student a lotof exibility$ fun and satisfaction ! %oryour child$ it means #ivin# them acompetitive ed#e$ a way to optimi&e their

performance and #ives them an ed#e inmathematics and lo#ic that will help themto shine in the classroom and beyond!


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'herefore it(s direct and easy toimplement in schools ) a reason behindits enormous popularity amon#

academicians and students!

"t complements the Mathematicscurriculum conventionally tau#ht inschools by actin# as a powerful checkin#tool and #oes to save precious time inexaminations!'he methods * techni+ues

are based on the pioneerin# work of late,wami ,hri Bharati -rishna 'irtha.i$,ankracharya of /uri$ who established thesystem from the study of ancient Vedictexts coupled with a profound insi#ht intothe natural process of mathematicalreasonin#!

'here are .ust 01 ,utras or %ormulae whichsolve all known mathematical problems inthe branches of 2rithmetic$ 2l#ebra$3eometry and 4alculus! 'hey are easy tounderstand$ easy to apply and easy toremember!

Vedic Mathematics is theworlds fastest way of making allyour maths calculations easy.

It is an ancient system of mathematics which was rediscoveredfrom the Vedas between 1911 & 1918 by Shri Bharti KishnaTirthaji (188 !19"#$. %ccording to his research all of Mathematics


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is based on 1" 'utras or ord )ormulae.

Benefits of Vedic Maths Eliminates math-phobia . Increases speed and accuracy .

More systematic, simplified, unified & faster than the conventional system.

*ives the student flexibility, fun andimmense satisfaction

% powerful checking tool .

a!es precious time in e+aminations.

*ives the student a competiti!e edge.

,evelo-s eft & /ight 'ides of the brains

by increasing !isuali"ation and concentration abilities.

V56 "ntroductionVerilo# is a 52 6 2 6 ,4 "/'";< 256 ?! 2hardware description lan#ua#e is a lan#ua#e used to describea di#ital system: for example$ a network switch$ a

microprocessor or a memory or a simple ip@ op! 'his .ustmeans that$ by usin# a 56 $ one can describe any >di#ital?hardware at any level!

0 AA 6 ip@ op 4ode module dCD > d$ clk$ +$ +Cbar?E F input d $clkE G output +$ +CbarE H wire d $clkE 1 re# +$ +CbarE 7

8 always I >posed#e clk? 9 be#in 0J + KL dE 00 +Cbar KL dE 0 end 0F0G endmodule


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;ne can describe a simple %lip op as that in the above #ure$ aswell as a complicated desi#n havin# 0 million #ates! Verilo# is one of the 56 lan#ua#es available in the industry for hardware desi#nin#!"t allows us to desi#n a 6i#ital desi#n at Behavior evel$ e#ister

'ransfer evel > ' ?$ 3ate level and at switch level! Verilo# allowshardware desi#ners to express their desi#ns with behavioralconstructs$ deferrin# the details of implementation to a later sta#ein the nal desi#n!

The Verilog Hardware Description Language, usually just called Verilog, was designed and firstimplemented by Phil Moorby at Gateway Design utomation in !"#$ and !"#%& 't was first used

beginning in !"#% and was e(tended substantially through !"#)& The implementation was theVerilog*+L simulator sold by GatewayHi'tor O* +eri(o,

erilog was started initially asa proprietary hardwaremodeling language byAateway /esign 3utomation

nc. around 19' . t isrumored that the originallanguage was designed byta=ing features from the mostpopular 4/H language of thetime, called 4iHo, as well asfrom traditional computer languages such as . 3t thattime, erilog was notstandardi>ed and thelanguage modified itself inalmost all the revisions thatcame out within 19' to1990.

erilog simulator was first

used beginning in 19'! andwas e tended substantiallythrough 19'&. Theimplementation was the

erilog simulator sold byAateway. The first ma8or e tension was erilogEKH,which added a few featuresand implemented theinfamous "KH algorithm"


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which was a very efficientmethod for doing gateElevelsimulation.

The time was late 1990.

adence /esign )ystem,whose primary product atthat time included Thin filmprocess simulator, decided toacIuire Aateway 3utomation)ystem. 3long with other Aateway products, adencenow became the owner of the

erilog language, andcontinued to mar=et erilogas both a language and a

simulator. 3t the same time,)ynopsys was mar=eting thetopEdown designmethodology, using erilog.This was a powerfulcombination.

n 1990, adence recogni>ed

that if erilog remained aclosed language, thepressures of standardi>ation

would eventually cause theindustry to shift to 4/H.onseIuently, adence

organi>ed the %pen erilognternational % ;, and in

1991 gave it thedocumentation for the erilog4ardware /escriptionHanguage. This was theevent which "opened" thelanguage.

% did a considerableamount of wor= to improvethe Hanguage -eference2anual H-2;, clarifyingthings and ma=ing thelanguage specification asvendorEindependent as


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possible.

)oon it was reali>ed that if there were too manycompanies in the mar=et for

erilog, potentially everybodywould li=e to do whatAateway had done so far Echanging the language for their own benefit. This woulddefeat the main purpose of releasing the language topublic domain. 3s a result in199 , the ### 1$6 wor=inggroup was formed to turn the% H-2 into an ###

standard. This effort wasconcluded with a successfulballot in 199!, and erilogbecame an ### standard in/ecember 199!.

*hen adence gave % theH-2, several companiesbegan wor=ing on erilogsimulators. n 199(, the firstof these were announced,

and by 199$ there wereseveral erilog simulatorsavailable from companiesother than adence. Themost successful of these was

), the erilog ompiled)imulator, from hronologic)imulation. This was a truecompiler as opposed to aninterpreter, which is what

erilogEKH was. 3s a result,compile time was substantial,but simulation e ecutionspeed was much faster.

n the meantime, the

popularity of erilog and


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admirers than wellEformedand federally funded 4/H. twas only a matter of timebefore people in % reali>edthe need of a more

universally acceptedstandard. 3ccordingly, theboard of directors of %reIuested ### to form awor=ing committee for establishing erilog as an

### standard. The wor=ingcommittee 1$6 was formedin mid 199$ and on %ctober 1 , 199$, it had its firstmeeting.

The standard, whichcombined both the eriloglanguage synta and the


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*ell am also going to show how to write a -%e((o$or(d- program, followed by a - o!nter- design, in erilog.

He((o or(d /ro,ra"

1 00

2 00 T%i' i' " *ir't +eri(o, /ro,ra" 3 00 e'i,n Na"e %e((o $or(d 4 00 Fi(e Na"e %e((o $or(d.v 5 00 F!n tion T%i' ro,ra" $i(( rint %e((o $or(d 6 00 oder ee a& 7 00 8 "od!(e hello_world ; 9

10 initia( #e,in 11 di' (a ( -He((o or(d # ee a&- ); 12 91: *ini'%; 13 end 14

15 end"od!(e 00 End o* Mod!(e %e((o $or(dGou could download file helloNworld.v here

*ords in green are comments, blue are reserved words.

3ny program in erilog starts with reserved word DmoduleDOmoduleNnameP. n the above e ample line ' containsmodule helloNworld. ?ote: *e can have compiler preEprocessor statements li=e QincludeD, QdefineD before moduledeclaration;

Hine 10 contains the initial bloc=: this bloc= gets e ecutedonly once after the simulation starts, at time+0 0ns;. Thisbloc= contains two statements which are enclosed withinbegin, at line 10, and end, at line 1$. n erilog, if you havemultiple lines within a bloc=, you need to use begin and end.2odule ends with DendmoduleD reserved word, in this case atline 1!.

He((o or(d /ro,ra" O!t !t

4ello *orld by /eepa=

o!nter e'i,n B(o &
http://www.asic-world.com/code/verilog_tutorial/hello_world.vhttp://www.asic-world.com/code/verilog_tutorial/hello_world.vhttp://www.asic-world.com/code/verilog_tutorial/hello_world.v


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o!nter e'i,n ; e '

Ebit synchronous up counter.

active high, synchronous reset.

3ctive high enable.

o!nter e'i,n

1 00 2 00 T%i' i' " 'e ond +eri(o, e'i,n 3 00 e'i,n Na"e *ir't o!nter 4 00 Fi(e Na"e *ir't o!nter.v 5 00 F!n tion T%i' i' a 4 #it ! o!nter $it% 6 00 ; n %rono!' a tive %i,% re'et and 7 00 $it% a tive %i,% ena#(e 'i,na( 8 00 9 "od!(e first_counter ( 10 clock , 00 (o & in !t o* t%e de'i,n

11 reset , 00 a tive %i,%< ' n %rono!' Re'et in !t 12 en !le , 00 A tive %i,% ena#(e 'i,na( *or o!nter 13 counter_out 00 4 #it ve tor o!t !t o* t%e o!nter 14 ); 00 End o* ort (i't 15 00 n !t /ort' 16 in !t clock ; 17 in !t reset ; 18 in !t en !le ; 19 00 O!t !t /ort' 20 o!t !t "3#0$ counter_out ; 21 00 n !t ort' ata T e 22 00 B r!(e a(( t%e in !t ort' '%o!(d #e $ire'

23$ire

clock ; 24 $ire reset ; 25 $ire en !le ; 26 00 O!t !t /ort' ata T e 27 00 O!t !t ort an #e a 'tora,e e(e"ent >re,) or a $ire 28 re, "3#0$ counter_out ; 29

30 00 ode ;tart' Here 31 00 ;in e t%i' o!nter i' a o'itive ed,e tri,,ed one


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32 00 e tri,,er t%e #e(o$ #(o & $it% re' e t to o'itive 33 00 ed,e o* t%e (o &. 34 a($a ' ? ( o'ed,e clock) 35 #e,in %&' *+ 00 B(o & Na"e 36 00 At ever ri'in, ed,e o* (o & $e %e & i* re'et i' a tive 37 00 * a tive< $e (oad t%e o!nter o!t !t $it% 4 #::::

38 i* (reset == 1 !1) #e,in 39 counter_out @= 91 4 !0000; 40 end 41 00 * ena#(e i' a tive< t%en $e in re"ent t%e o!nter 42 e('e i* (en !le == 1 !1) #e,in 43 counter_out @= 91 counter_out 1; 44 end 45 end 00 End o* B(o & O NTER 46

47 end"od!(e 00 End o* Mod!(e o!nter Gou could download file firstNcounter.v here

o!nter Te't Ben % 3ny digital circuit, no matter how comple , needs to betested. For the counter logic, we need to provide cloc= andreset logic. %nce the counter is out of reset, we toggle theenable input to the counter, and chec= the waveform to seeif the counter is counting correctly. This is done in erilog.

The counter testbench consists of cloc= generator, resetcontrol, enable control and monitor@chec=er logic. elow isthe simple code of testbench without the monitor@chec=er logic.

1 Cin (!de -*ir't o!nter.v- 2 "od!(e first_counter_t!(); 3 00 e (are in !t' a' re,' and o!t !t' a' $ire' 4 re, clock, reset, en !le; 5 $ire "3#0$ counter_out; 6

7 00 nitia(iDe a(( varia#(e'
http://www.asic-world.com/code/verilog_tutorial/first_counter.vhttp://www.asic-world.com/code/verilog_tutorial/first_counter.v


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8 initia( #e,in 9 di' (a ( -ti"e t (& re'et ena#(e o!nter- );

10 "onitor ( - , t # # # #- ,11 ti"e , clock, reset, en !le, counter_out);

12 clock = 1; 00 initia( va(!e o* (o & 13 reset = 0; 00 initia( va(!e o* re'et

14 en !le = 0; 00 initia( va(!e o* ena#(e 15 95 reset = 1; 00 A''ert t%e re'et 16 91: reset = 0; 00 e a''ert t%e re'et 17 91: en !le = 1; 00 A''ert ena#(e 18 91:: en !le = 0; 00 e a''ert ena#(e 19 95 *ini'% ; 00 Ter"inate 'i"!(ation 20 end 21

22 00 (o & ,enerator 23 a($a ' #e,in 24 95 clock = Gclock; 00 To,,(e (o & ever 5 ti &' 25 end 26

27 00 onne t T to te't #en % 28 first_counter '_counter ( 29 clock, 30 reset, 31 en !le, 32 counter_out 33 ); 34

35 end"od!(eGou could download file firstNcounterNtb.v here

time cl= reset enable counter

0 1 0 0 ! 0 1 0 10 1 1 0 11 1 1 0 0000 1! 0 0 0 0000 (0 1 0 0 0000 (! 0 0 1 0000 $0 1 0 1 0000 $1 1 0 1 0001 $! 0 0 1 0001 0 1 0 1 0001 1 1 0 1 0010 ! 0 0 1 0010 !0 1 0 1 0010 !1 1 0 1 0011 !! 0 0 1 0011 60 1 0 1 0011 61 1 0 1 0100 6! 0 0 1 0100 &0 1 0 1 0100 &1 1 0 1 0101 &! 0 0 1 0101 '0 1 0 1 0101
http://www.asic-world.com/code/verilog_tutorial/first_counter_tb.vhttp://www.asic-world.com/code/verilog_tutorial/first_counter_tb.v


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'1 1 0 1 0110 '! 0 0 1 0110 90 1 0 1 0110 91 1 0 1 0111 9! 0 0 1 0111 100 1 0 1 0111 101 1 0 1 1000 10! 0 0 1 1000 110 1 0 1 1000 111 1 0 1 1001 11! 0 0 1 1001 1(0 1 0 1 1001 1(1 1 0 1 1010 1(! 0 0 0 1010

o!nter ave*or"

Mod!(e'

2odules are thebuilding bloc=s of

erilog designs

Gou create the designhierarchy byinstantiating modulesin other modules.

/ort'


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have ports.

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