La Investigación generadora de riqueza

WINCO`05

México D.F., México, 13 de Abril de 2005

Prof. Mateo Valero, UPC, Barcelona

2

Outline

High Performance Research Group at UPC

Centers of Supercomputing: CEPBA CIRI BSC

Future context in Europe Networks of Excellence Large Scale Facilities

3Erkki Liikanen Brussels, 21 April 2004

4Erkki Liikanen Brussels, 21 April 2004

5Erkki Liikanen Brussels, 21 April 2004

6

Basic concepts about research Fundamental/basic research versus applied research Good versus bad research Good research produces always wealth

Short/Medium/Long Term Research Products of good research:

Papers and patents Educated people

Good education is a key component in this picture Cross-Pollination between Research groups and

companies are the other part of the movie To promote good research is the only way Europe has to

be competitive in a short/long future

7

Historia

Tesis: 1974-1980 Mucha dificultad

FIB Crear departamento: asignaturas, contratar,.. Empezar a investigar Situación española… no hay $, no existe nada,…

CICYT

Decisiones Estratégicas: Arquitectura de Computadores Supercomputadores

8

Computer Architecture

Computer Architecture is a rapidly changing subject Technology changes very fast New applications emerge continuously

Computer Architects must deal with both technology and applications CMOS Technology is coming to an end A new group of applications is appearing

There is a great opportunity for high performance architectures for these applications

9

Supercomputers

Faster computers in the world Used to simulate Mainly fabricated by USA companies No experience in Spain Europe uses and produces software

10

Entrada de España en la EU

Internacionalización de la Investigación

Nuevas oportunidades Antes y despues de 1986 Proyectos industriales Usamos estos proyectos para crecer en

investigación básica

11

CICYT: Spanish Projects

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004

Parallelism Exploitation in

High Speed Architectures

TIC89-299

Architecture, Tools and Operating Systems for

Multiprocessors

TIC89-392

HLL-orientedArchitectures

TIC89-300

High Performance Computing II

TIC98-511-C02-01

UdZ, URVand ULPGC

High Performance Computing III

TIC2001-995-C02-01

UVall

Architectures and Compilers

for Supercomputers

TIC92-880

Parallel Architecturesfor Symbolic Computation

TIC91-1036

High Performance Computing

TIC95-429

Microkernel/applicationsCooperation in

Multiprocessor Systems

TIC94-439

High Performance Computing IV

TIC2004-7739-C02-01

12

People: large research group

79 researchers 34 PhD 45 doing PhD

6

25

53

21

19

Full

Associate PhD

Associate noPhD

Assist PhD

Assist no PhD

PhD student

Now

13

Research topics and target platforms

Task Subtask Target architecture

T1: Computer architecture

T1.1: Processor microarchitecture SP

T1.2: Memory hierarchy SP and small MP

T1.3: Code generation and optimization

SP

T2: Compilers, execution environments and tools

T2.1: Sequential code optimization SP

T2.2: OpenMP All MP

T2.3: Extensible execution environments

All MP and GRID

T2.4: Tools All MP and GRID

T3: Algorithms and applications

T3.1: Numerical applications All of them

T3.2: Non-numerical applications SP and small MP

T3.3: Distributed applications All MP and GRID

14

Computer architecture (uniprocessor)

Dynamically scheduled (superscalar) Front-end engines: instruction fetch mechanisms and

branch predictors Speculative execution: data and address prediction Organization of resources:

• Register file, functional units, Cache organization, prefetching …

Kilo-instruction Processors Not only performance: area and power consumption

15

Computer architecture (uniprocessor)

Statically scheduled (VLIW) Organization of resources (functional units and

registers) Not only performance: area and power consumption

Advanced vector and multimedia architectures Vector units for superscalar and VLIW architectures Memory organization Data and instruction level parallelism

16

Computer architecture (multiprocessor)

Multithreaded (hyperthreaded) architectures Front-end engines and trace caches Speculation at different levels Dynamic management of thread priorities

Shared-memory multiprocessors Memory support for speculative parallelization

(hardware and software)

17

System software (multiprocessor)

OpenMP compilation Proposal of language extensions to the standard Compiler technology for OpenMP

OpenMP runtime systems Parallel library for OpenMP (SGI Origin, IBM SP2, Intel

hyperthreaded, …) Software DSM (Distributed Shared Memory) Intelligent runtimes: load balancing, data movement, …

18

System software (multiprocessor)

Scalability of MPI IBM BG/L with 64K processors Prediction of messages

Programming models for the GRID Grid superscalar

19

Algorithms and applications

Solvers for linear equations systems Out-of-core kernels and applications STORM

Metacomputing tool for performing stochastic simulations Data bases

Sorting, communication in join operations Query optimization Memory management in OLTP

20

PhD programs

Research topics are part of our PhD programs

Computer Architecture and Technology at UPC Quality award: MCD2003-126 42% total number of credits, 2003-04 30 PhD in the last 5 years (66% of whole program)

21

International collaboration

Industry Intel, IBM Watson, Toronto, Haifa and Germany Labs (*),

Hewlett-Packard, STMicroelectronics, SGI, Cray, Compaq University and research laboratories

Univ. of Illinois at Urbana-Champaign, Wisconsin-Madison, California at Irvine, William and Mary, Delft, KTH, … (more than 60)

Major research laboratories in USA: NASA Ames, San Diego (SDSC), Lawrence Livermore (LLNL), …

Standardization committees OpenMP Futures in the Architecture Review Board (ARB)

… with joint publications and developments

(*) Part of the CEPBA-IBM Research Institute research agreement

22

International collaboration

Pre- and post doctoral short/medium/long stays Industry: Intel, SUN, IBM, Hewlett-Packard, ... University: Univ. of Illinois at Urbana-Champaign,

Univ. of California at Irvine, Univ. of Michigan, ...

Visiting professors and researchers More than 70 talks in our weekly seminar (last two

years, external researchers)http://research.ac.upc.es/HPCseminar/

PhD courses:• 2001-02: 5 courses (135 hours)• 2002-03: 4 courses (110 hours)• 2003-04: 6 courses (165 hours)

23

Some of the seminar guestsKrste Asanovic (MIT)Venkata Krishnan (Compaq-DEC)Trevor Mudge (U. Michigan)Jim E. Smith (U. Wisconsin)Luiz A. Barroso (WRL)Josh Fisher (HP Labs)Michel Dubois (USC)Ronny Ronnen (Intel, Haifa)Josep Torrellas (UIUC)Per Stenstrom (U. Gothenburg)Wen-mei Hwu (UIUC)Jim Dehnert (Transmeta)Fred Pollack (Intel)Sanjay Patel (UIUC)Daniel Tabak (George Mason U.)Walid Najjar (Riverside)Paolo Faboroschi (HP Labs)Eduardo Sánchez (EPFL)Guri Sohi (U. Michigan)Jean-Loup Baer (Washington Uni.)

Miron Livny (U. Wisconsin)Tomas Sterling (NASA JPL)Maurice V. Wilkes (AT&T Labs)Theo Ungerer (Karlsruhe)Mario Nemirovsky (Xstreamlogic)Gordon Bell (Microsoft)Timothy Pinkston (U.S.C.)Walid Najjar (Riverside)Roberto Moreno (ULPGC)Kazuki Joe (Nara Women U.)Alex Veidenbaum (Irvine)G.R. Gao (U. Delaware)Ricardo Baeza (U.de Chile,Santiago)Gabby M. Silberman (CAS-IBM)Sally A. McKee (U. Utah)Evelyn Duesterwald (HP-Labs)Yale Patt (Austin)Burton Smith (Tera)Doug Carmean (Intel, Oregon)David Baker (BOPS)

24

International collaboration

Mobility programs (*)

Access: Transnational Access for Researchers (2000-03)

Access-2: Transnational Access for Researchers (2002-04)

Networks of Excellence HIPEAC: High-Performance Embedded Architectures

and Compilers, in evaluation (www.hipeac.org) CoreGRID (*): middleware for GRID, in evaluation

(*) Projects of the European Center for Parallelism of Barcelona

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Industrial technology transfer European projects (IST and FET)

INTONE: Innovative OpenMP Tools for Non-experts (2000-03) DAMIEN: Distributed Applications and Middleware

for Industrial use of European Networks (2001-03) POP: Performance Portability of OpenMP (2001-04) Antitesys: A Networked Training Initiative for Embedded

Systems Design (2002-04)

Attract international companies to establish branches

or laboratories in Barcelona EASi Engineering: S. Girona (*)

Intel Labs: R. Espasa (*) and T. Juan (*), A. Gonzalez (*), Hewlett-Packard Labs

(*) Professors of the Computer Architecture Department (full or part time dedication)

26

Industrial Relationships Compaq

Sabbaticals• Roger Espasa (VSSAD)• Toni Juan (VSSAD)• Marta Jimenez (VSSAD)

Interns• Jesus Corbal (VSSAD)• Alex Ramirez (WRL)

Partnerships• BSSAD

HP Sabbaticals

• Josep Llosa (Cambridge) Interns

• Daniel Ortega• Javier Zalamea

Parnerships• Software Prefetching• Two-Level Register File

Sun Microsystems Interns

• Pedro Marcuello• Ramon Canal• Esther Salami• Manel Fernande

Microsoft

IBM Interns

• Xavi Serrano (CAS)• Daniel Jimenez (CAS)• 3 more people in 2001

Parnerships• Supercomputing (CIRI)• Low Power • Databases • Binary Translation

Faculty Awards Intel

Interns• Adrian Cristal (Haifa)• Alex Ramirez (MRL)• Pedro Marcuello (MRL)

Parnerships• Semantic Gap• Smart Registers• Memory Architecture for Multithreaded

Processors• Speculative Vector Processors

Labs in Barcelona MRL and BSSAD Advisory Board of MRL

Xstream, Flowstorm, Kambaya Advising committee

ST- Microelectronics Analog Devices

27

Conclusions

Large (90) team with experience in many topics Computer architecture System software Algorithms and applications

Good production >100 PhD thesis Publications in top conferences (>400) and journals

(>150) Prototypes (3) used in research laboratories 25 professionals in industry

Long track of international collaborations Academic Industrial

28

Outline High Performance Research Group at UPC

Centers of Supercomputing: CEPBA CIRI BSC

Future context in Europe Networks of Excellence Large Scale Facilities

Conclusions

Centro Europeo de Centro Europeo de Paralelismo de BarcelonaParalelismo de Barcelona

CEPBACEPBA

30

CEPBA

DAC

• HPC experience

Depts. CER

• October 1991

• R+D on parallelism

• Training

•Technology transfer

• European context

CEPBA

RME, LSI, FEN, FA

• Computing needs

31

CEPBA Activities

• Service

• Training

• Technology transfer

– T.T. Management

– R & D–24 proyectos

Technological expert

Developments

32

Service

COMPAQ12 alpha 21164SMP2GB Mem32 GB Disk

SGI64 R10000CC-NUMA8GB Mem 360 GB Disk

• Access• Users support

Parsytec16 Pentium II

2CPUs nodes3 Networks

Fast EthernetMyrinetHS link

1GB Mem 30 GB Disk

IBM64 Power3Net. SMP32GB Mem 400 GB Disk

33

Proyect Period Funding Visitors UPCHCM 1993-1997 950 112 49

PECO 1995-1996 160 17 15

TMR 1996-2000 935 133 46

IHP 2000-2003 700 28 8

2745 290 118Total

European Mobility Programs

Joint CEPBA - CESCA projects Stays and access to resources

34

Technology Transfer

R+D projects

Technology Transfer Management

1986... 1994 1995 1996 19971991...

CEPBA

23Projects

3 cluster projects28 Subprojects

Technical management & Dissemination

Technological partner & developments

19991998 2000...

35

Metacomputing

System

Tools

R&D Projects

Supernode II

94 95 96 979392 98 99 00

Dimemas & Paraver

Identify

Permpar Parmat Asra

Promenvir Promenvir+

DDT

Hipsid

NanosApparc

Phase

Bonanova

Sloegat

BMW

Sep-tools

01

Parallelization

ST-ORM

Intone

Damien

36

T.T. Management

35 Proposals28 projects

Promote proposals to EC

Technical management of projects

Dissemination

1994 1995 1996 1997 1998 1999 2000

CEPBA-TTN

PCI-PACOS

PCI-II

PACOS 2

37

PCI-PACOS

AMESCIMNE

Metodos Cuantitativos Gonfiesa

CESCACESGA

HesperiaNeosystems

UPC-EIO

IberdrolaUitesa

UPV

AZTIUPC-LIM

Ayto. BarcelonaUitesaUPC-EIO

TGIUPM-DATSI

TecnatomUMA

38

PCI-II

ItalecoGeospaceIntecsUniv. Leiden

Ospedali Galliera Le MolinetteParsytecPACEDS

ENELEDFCSR4ReiterKenijoki

FerrariGenias

P3C

Cari VeronaAISPACUniv. Cat. Milan

VolkswagenRicardoPAC

Inisel EspacioInfocartoUPC-TSCCEPBA-UPC

CANDEMAT CIMNECEPBA-UPC

Intera SPIntera UKUPC-DITCEPBA-UPC

Cristaleria EspañolaUNICANCEPBA-UPC

39

HPCN TTN network

40

CEPBA-TTN

TorresSoftware Greenhouse CEPBA-UPC

BCN COSIVERMides

UPC-EIO

CEBAL-ENTECNEOSYSTEMS

Soler y PalauCIMNECEPBA-UPC

CASAEnvisionGTDIntespaceRUS

CEPBACESCAUMAUNICANUPM

SENERCICUNICAN

IberdrolaSAGECEPBA-UPC

INDOCEPBA-UPC

ST MecanicaDERBIAUSACEPBA-UPC

41

References: Technology promotion

AMESAUSAINDOAyto. BCNBCN COSIVERCEBAL-ENTECDERBIHESPERIAMétodos CuantitativosMidesNEOSYSTEMSQuantiSci SLSoftware GreenhouseSoler y PalauST MecánicaTorres

AISCariVeronaEDF-LNHEDS ItalyENEL-CRISFerrari AutoGeniasGeospaceIntecs SistemiIntespaceItalecoKemijokiLe MolinetteOspedali GallieraParsytecQuantiSci LTDReiterRicardoVolswagen

CESCACESGACIMNECRS4P3CPACRUS

Catholic Univ. MilanPolitecnico di MilanoUNICAN UPMUMAUniv. of LeidenUPC-DITUPC-EIOUPC-LIMUPC-OEUPC-RMEUPC-TSCIPM-DATSIUPV

AZTICandematCASACICCristaleria EspañolaEnvisonGonfiesaGTDIberdrolaIndra EspacioInfocartoSAGESENERTecnatomTGIUitesa

European Comission

42

Budget (PACOS,PCI-II,TTN)

Managed ESPRIT Funding:11.8 Mecus (total)

Distribución

Gestión CEPBA

Técnico CEPBA

Resto UPC

Resto CAT

Resto SP

Resto EU

43

CEPBA-IBM Research Institute

44

CIRI’s mission

CEPBA-IBM Research Institute (CIRI) was a research and development partnership between UPC and IBM.

•Established in October 2000 with an initial commitment of four years.

•Its mission was to contribute to the community through R&D in Information Technology.

•Its objectives are: Research & Development

External R&D Support

Technology Transfer

Education

•CEPBA (European Center for Parallelism Barcelona) was a deep computing research center, at the Technical University of Catalonia (UPC), which was created in 1991.

45

Organization

Management and Technical Boards evaluate project performance and achievements and recommend future directions.

70 people were collaborating with the Institute:

Board of Directors (4) Institute’s Professors (10) Associate Professors (9) Researchers (5) PhD Students (21) Graduate Students (3) Undergraduate Students (18)

46

Deep Computing Performance Tools: Numerical Codes Web Application Servers Parallel Programming Grid Code Optimization

Computer Architecture Vector Processors Network Processors

Data Bases Performance Optimization DB2 Development & Testing

Introduction: CIRI areas of interest

47

CIRI R&D Philosophy

OpenMP•OMPTrace

•activity•hw counters

•Nested Parallelism•Precedences•Indirect access

Performance Visualization

Paraver

Dimemas•Collective, mapping•Scheduling

System scheduling•Self analysis•Performance Driven Proc. Alloc.•Process and memory control

RunTime Scheduling•Dynamic load balancing•Page migration

MPI•UTE2paraver•OMPITrace

Applications•Steel stamping•Structural analysis•MGPOM•MPIRE

Metacomputing•ST-ORM

Technology Web

ComputerArchitecture

BarcelonaSupercomputingCenterCentro Nacional de Supercomputación

Professor Mateo Valero

Director

Theory

Experiment

Computing& Simulation

High

Performance

Computing

Aircraft,Automobile Design

Fusion Reactor,Accelerator Design,

Material Science,Astrophysics

Climate and Weather Modeling

What drives

HPC ? “The

Need for

Speed...”

Computational Needs of Technical, Scientific, Digital Media and Business ApplicationsApproach or Exceed the Petaflops/s Range

CFD Wing Simulation512x64x256 Grid(8.3 x10e6 mesh points)5000 FLOPS per mesh point,5000 time steps/cycles2.15x10e14 FLOPS

CFD Full Plane Simulation512x64x256 Grid(3.5 x10e17 mesh points)5000 FLOPS per mesh point,5000 time steps/cycles8.7x10e24 FLOPSSource: A. Jameson, et al

Materials Science

Magnetic Material: Current: 2000 atoms; 2.64 TF/s, 512 GB Future: HDD Simulation - 30 TF/s, 2 TBElectronic Structures: Current: 300 atoms; 0.5 TF/s, 100 GB Future: 3000 atoms; 50 TF/s, 2TB

Source: D. Balley, NERSC

Digital Movies and Special Effects

~1e14 FLOPs per frame50 frames/sec90 minute movie - 2.7e19 FLOPs

~ 150 days on 2000 1GFLOP/s CPUs

Source: Pixar

Spare Parts Inventory Planning

Modelling the optimized deployment of 10000 part numbers across 100 part depots and requries:- 2x10e14 FLOP/s (12 hours on 10, 650 MHz CPUs)- 2.4 PetaFlop/s sust. performance (1 hour turn-around time)Industry trend to rapid, frequent modeling for timely business decision support driver higher sustained performance

Source: B. Dietrich, IBM

Applications for

Supercomputers

Aircraft/car simulations Life Science (Proteins, Human Organs,…) Atmosphere Stars Nanomaterials Drugs Regional/Global Climate/Weather/Pollution High Energy Physics Combustion Image Processing

Suitable applications for

massively parallel systems

Source: Rick Stevens,Argonne National Lab andThe University of Chicago

Significant contribution to advancement of Science in Spain, enabling supercomputing capacity, scientific-technical synergies, and cost rationalization thanks to economies of scale

Powerful tool to assist research and development centers, public and private, generating impulses for a new technological environment

Motivation

Mission

”Investigate, develop and manage technology to facilitate the advancement of science”

Objectives

Research in Supercomputing and Computer Architecture

Collaborate in R&D e-Science projects with prestigious scientific teams

Manage BSC supercomputers to accelerate relevant contributions to research areas where intensive computing is an enabling technology

57

Dirección de Tecnologías

de la Información

Dirección deDesarrollo de

Negocio

DirecciónAdministración

y Finanzas

Dirección de

Biomedicina

y Ciencias

de la Vida

Dirección de Química y Ciencia de

los Materiales

Dirección de Física e

Ingeniería

Dirección de Operaciones

CONSEJO RECTOR

Presidencia

Comisión Ejecutiva PATRONATO

Director AsociadoDirector

I+D en I.T.

e-Ciencia

Gestión

Comisión Científica Asesora

Comité de Acceso

Dirección de

Astronomia y

Espacio

Dirección deCiencias

de la Tierra

Organización del BSC

IT research and development projects

Continuation of CEPBA (European Center for Parallelism in Barcelona) research lines

Deep Computing Performance Tools Parallel programing Grid Code Optimization Computer Architecture Vector processors Network processors

e-Science projects

R&D collaborations

Computational Biology

Computational Chemistry

Computational Physics

Information based Medicine

Management projects

Supercomputer Management

System Administration

Users support

Business Development

External Relations

Promotion

Technology Transfer

Education

Administration

Accounting and Finances

Human Resources

MareNostrum

PowerPC 970 FX processors (dual processors)

4GB ECC 333 DDR memory per node

3 networks

Myrinet

Gigabit

10/00 Ethernet

Diskless network support

Linux cluster

27 Compute Racks (RC01-RC27)• 162 BC chassis w/OPM and gigabit ether switch• 2268 JS20+ nodes w/myrinet daughter card

7 Storage Server Racks (RS01-RS07)• 40 p615 storage servers 6/rack• 20 FastT 100 3/rack• 20 EXP100 3/rack

4 Myrinet Racks (RM01-RM04)• 10 clos256+256 myrinet switches• 2 Myrinet spines 1280s

1 Gigabit Network Racks• 1 Force10 E600 for Gb network• 4 Cisco 3550 48-port for 10/100 network

1 Operations Rack (RH01)• 7316-TF3 display• 2 p615 mgmt nodes• 2 HMC model 7315-CR2• 3 Remote Async Nodes• 3 Cisco 3550• 1 BC chassis (BCIO)

MareNostrum:

System description

Processor:

PowerPC 970FX

JS20 Processor Blade• 2-way 2.2 GHz Power PC 970 SMP• 4GB memory (512KB L2 cache)• Local IDE drive (40 GB)• 2x1Gb Ethernet on board• Myrinet daughter card

Blade Center• 14 blades per chassis (7U)

• 28 processors• 56GB memory

• Gigabit ethernet switch

Blades, blade center and racks

6 chassis in a rack (42U)• 168 processors• 336GB memory

Blade centers

Myrinet racks

Storage servers

Operations rack

Gigabit switch

10/100 switches

MareNostrum:

Floor plan

with cabling

27 racks + 1 BC chassis • 4564 processors• 9TB memory

Blade centers

Myrinet racks

Storage servers

Operations rack

Gigabit switch

10/100 switches

256 blades connected to 1 clos 256+256 Myrinet

1280 blades connected to 5 clos 256+256 Myrinet and 1 spine 1280

2282 blades connected to 10

clos 256+256 Myrinet and 2 spine 1280

20 x 7TB storage nodes

Management rack, Force 10

Gigabit, 10/100 Cisco

switches

Blade center racks

6 Blade Centers per rack

27 racks + 1 Blade Center

Cabling per rack

84 fiber cables to myrinet switch

6 Gb to Force10 E600

6 10/100 cat5 to Cisco

Blade Center

Blade Center

Blade Center

Blade Center

Blade Center

Blade Center

Myrinet racks

10 Clos 256x256 switches

Interconnect up to 256 Blades

Connect to Spine (64 ports)

2 Spine 1280

Interconnect up to 10 Clos 256x256 switches

Monitoring using 10/100 connection

Spine 1280Clos 256x256

256 Bladesor Storage servers

64 to Spine

320 from Clos

Myrinet racks

Interconnection of Blade Centers

Used for system boot of every blade center

212 internal network cables

170 for blades

42 for p615

76 connection available to external connection

Gb

Subsystem:

Force 10

E600

Storage

nodes

Total of 20 storage nodes, 20 x 7 TBytes

Each storage node

2xP615

FastT100

EXP100

Cabling per node

2 Myrinet

2 Gb to Force10 E600

2 10/100 cat5 to Cisco

1 Serial

P615P615

FastT100EXP100

P615P615

FastT100EXP100

P615P615

FastT100EXP100

Management rack

Contents

BCIO

Display

2 HMC

2 x p615

3 x Cisco

3 x 16-port Remote Async Nodes

74

Mare Nostrum Supercluster

Myrinet or Infiniband interconnect

Gigabit Ethernet Interconnect

IBM

IBM

Ebro TiberisRhodanus

HispaniaData

Server

BarcinoSystem

Gateway

Nilus

TarracoVisualization

Cluster

ePOWERUser Community

ThreeRivers

contractboundary

MareNostrum

81

Outline

High Performance Research Group at UPC

Centers of Supercomputing: CEPBA CIRI BSC

Future context in Europe Networks of Excellence Large Scale Facilities

82Erkki Liikanen Brussels, 21 April 2004

83

Future

Networks of Excellence HiPEAC InSyT

European FP VII Technology Platforms Large Scale Facilities

DEISA

84

HiPEAC Objectives

to help companies identify and select the best architecture solutions for scaling up high-performance embedded processors in the coming years

to unify and focus academic research efforts through a processor architecture and compiler research roadmap

to address the increasingly slow progression of sustained processor performance by jointly developing processor architecture and compiler optimizations

to explore novel approaches for achieving regular and smooth scaling up of processor performance with technology, and to explore the impact of a wide range of post-Moore's law technologies on processor architecture and programming paradigms.

85

Partners

Chalmers University, SwedenCNRS, FranceDelft University, The NetherlandsEdinburgh University, UKGhent University, BelgiumINRIA, FranceUniversity of Augsburg, GermanyUniversity of Patras, GreeceUniversity of Pisa, ItalyUPC Barcelona

STMicro, SwitserlandInfineon, GermanyEricsson, SwedenVirtutech, SwedenIBM Haïfa, IsraelKayser Italia, ItalyPhilips Research, The Netherlands

Leading partner per country

Industrial

86

HIPEAC Topics

Compiler optimizations Common compiler platform Processor architecture

Processor performance Power-aware design Real-time systems Special purpose architectures Multithreading and multiprocessors Dynamic optimization

Common simulation platform New processor paradigms

87

FET Programme FET is the IST programme nursery of novel and

emerging scientific ideas. Its mission is to promote research that is of a long-term nature or involves particularly high risks, compensated by the potential of a significant societal or industrial impact.

As such, FET is not constrained by the IST programme priorities but rather aims to open new possibilities and set new trends for future research programmes in Information Society Technologies.

FET goals will be achieved in two ways: Via the proactive scheme: a 'top down' approach which

sets the agenda for a small number of strategic areas holding particular promise for the future, and

Via the open scheme: a 'roots up' approach available to a wider range of ideas

88

FET: Advanced Computing Architectures

Critical mass Coordinate research by leading European groups

Education High quality European PhD program

Cross-pollination industry-academia Fuel industry with European students Feedback academia with real problems

Avoid emigration of specialists European students recruited by European companies Attracts IT companies to Europe

89

Future Emerging Technologies

Make Europe leader in microprocessor design

Support advanced research in Computer architectures Advanced compilers Micro-kernel operating systems

Targets 10+ year horizon 10x to 100x performance increase 10x power reduction

90

10+ year Horizon Future

CMOS technology will continue to dominate the market for the next 25 years However, we must be ready for CMOS alternatives

• Quantum computing, Molecular computing, …

Europe is well positioned in embedded processors, applications and technology Tomorrow’s embedded processor are today’s high-

performance processors

Europe need to remain the leader in the future embedded domain

91

FET Topics

Emerging architectures System on a Chip architectures (SoC) Chip Multiprocessors (CMP) Reconfigurable logic

Supporting technology Compiler optimizations Operating system level integration

Key elements Reduce design and verification effort Develop infrastructure for system and application

development Reuse of system architectures for wide range of

targets

92

Future

Networks of Excellence HiPEAC InSyst

IP projects, SCALA European FP VII Technology Platforms Large Scale Facilities

DEISA

Muchas Gracias