VMEBus, VXS, XMC, VPX · • VITA 41.1 VXS : Infiniband Protocol Layer • VITA 41.2 VXS : Serial...

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세미나VMEBus, VXS, XMC, VPX


목 차

VITA Specification --- 3 Page

VME Bus --- 4 ~ 20 Page

VITA 41 “VXS” --- 21 ~ 25 Page

VITA 42 “XMC” --- 26 ~ 29 Page

VITA 46 “VPX” --- 30 ~ 37 Page


VITA[vee-tuh]• VITA 1.0 VME64 Base• VITA 1.1 VME64x Extensions• VITA 17.2 10Gbit Serial FPDP• VITA 41.0 VXS : VME Switched Serial Base• VITA 41.1 VXS : Infiniband Protocol Layer• VITA 41.2 VXS : Serial RapidIO Protocol Layer• VITA 41.4 VXS : PCI Express Protocol Layer• VITA 42.0 XMC : Switched Mezzanine Card Base• VITA 42.3 XMC : PCI Express Protocol Layer• VITA 46 VPX : Base• VITA 48 VPX REDI :Enhanced Ruggedized Design Implementation

Mechanical Base• VITA 65 OpenVPX : Architectural Framework for VPX

VITA Specification


컴퓨터버스표준이다. 1979년대후반에모토로라가칩을개발하면서공개한 Versa 버스를유럽의전자업체에의해재탄생.

Versa Module Eurocard Bus의시작후많은업체들이사용. IEEE 위원회에서공식적으로 표준화.

산업체, 상업적, 군사적으로널리사용

연도 최대속도(Mbyte/초)

VME Bus32 1981 40

VMEbus IEEE -1014 1987 40

VME64 1994 80

VME64x 1997 160

VME320 1997 320

VME Bus


VME Bus


VME Bus Structures 1


VME Bus Structures 2


분홍색 : Data Transfer Signals 빨간색 : Arbitration Signals 파란색 : Priority Interrupt Signals 보라색 : Utility Signals

VME Signals

Signal Name Description Signal Name Description

A01-A31 Address Bus DTACK* Data Acknowledge

ACFAIL* AC Power failure IACK* Interrupt Ack.

AM0-AM5 Address Modifier IACKIN* Interrupt Ack.

AS* Address Strobe IACKOUT* Interrupt Ack.

BBSY* Bus Busy IRQ1*-IRQ7* Interrupt Request

BCLR* Bus Clear LWORD* LongWord

BERR* Bus Error SERCLK Serial Clock

BG0IN*-BG3IN* Bus Grant In/Out(daisy-chain)

SERDAT* Serial Data

BG0OUT*-BG3OUT* SYSCLK* System Clock

BR0*-BR3* Bus Request SYSFAIL* System Failure

D00-D31 Data Bus SYSRESET* System Reset

DS0*-DS1* Data Stribe WRITE* Write


• AM(Address Modifier)로 4비트(not used), 8비트(거의사용안하나특수영역에서사용), 16비트, 24비트, 32비트, 64 address결정

Address Bus


• Two Data Strobe[DS1..DS0], Address bit[A02..A01] 과 LWORD를사용하여 Data Bus Width을결정

Data Bus


• Address Timing Data Timing

Bus Timing 1


• Address/Data Timing Block Transfer Timing


• VME Arbitration 방법① 우선순위방식 --- BR3*>BR2*>BR1*>BR0*② Round-robin 방식 --- BR3*>BR2*>BR1*>BR0*>BR3*③ VMEbus 릴리스방식 --- RWD(Release When Done) 요청기사용④ ROR(Release on Request)⑤ 우선 Interrupt Bus Lines

Arbitration Bus


VME Product 구조


Pin Assign (P1/J1, P2/J2)


P0 Pin Assign(VME64*)


Board Size 1


Board Size 2


• 21 Slot 6U for 19” racks• 다양한 Power Supply (5V, +/- 12V, 3.3V, 48V)• Termination --- backplane 종단으로부터의 reflection 감소,

Open-collector driver에 pull-up 저항을달아 신호라인을 high state로유지• Dasiy Chain --- Ring Toplology : Loop connection back from the last device • to the first•

Rack System


Back Planes

VME64x VITA41 VITA46


VME64x, V41, V46.1 Pin-out


VITA 41 “VXS”

– VITA 41.0 base standard• Completed, drawings being updated• Defines physical features that enable high-speed

communication in a VME compatible system

– Protocol mappings• VITA 41.1 Infiniband; completed• VITA 41.2 Serial RapidIO®; completed• VITA 41.3 Ethernet; in process• VITA 41.4 PCI Express; in process• VITA 41.11 RTM (Rear Transition Module); in process


VITA 41 “VXS”

• Replace existing P0 with Multi-Gig RT2 7-Row

• Add switch slots using all Multi-Gig RT2 9-Row

• Upside– Backward compatibility with P1, P2 DIN connectors

• Downside– Not compatible with boards using existing P0 2mm connector– Limited number of high-speed pins in new P0 Multi-Gig connector– Connectors not 2-level maintenance ready– 3U format does not benefit from new P0 connector thus no allowance

for high-speed signaling upgrades


Multiple high-speed differential signaling

• 6U VME64 카드에 P0 connector 추가


P0 Sample(Serial RapidIO)


VITA 42 “XMC”

– VITA 42.0 base standard• A high-speed switched interconnect• Open, standardized technologies for switche fabrics• Standard PMC form factors• PMC, XMC, or dual-mode mezzanine cards• PMC, XMC, or dual-mode carriers• Standard VME, CompactPCI, Advanced TCA, and PCI Express carriers• Standard PCM stacking heights• Optional conduction cooling

– Protocol mappings• VITA 42.1 Parallel RapidIO; completed• VITA 42.2 Serial RapidIO; completed• VITA 42.3 PCI Express; completed• VITA 42.10 general purpose I/O; in process


P15 Primary XMC Connector(19x6, 114pins)• 20 different high-speed pairs • I2C, JTAG, reset• System Management• 3.3V Power : 4 pins, 1A/pin, 13.2W• Variable Power : 8 pins, 1A/pin

P16 Secondary XMC Connector(19x6, 114pins)• 20 high-speed different pairs • 38 user-defined pins for I/O

• Mapping for PCI Express

XMC


• Four 64pins, 10mm• Pn1(Pn0)-Pn2(Pn4) : Provides 32bit PCI

(132MByte/s)• Pn3 : Allows 64bit PCI(264MByte/s)• Pn4: Provides for 64bits User Defined I/O

PMC


PMC


VITA 46 “AMF”

– VITA 46.0 base standard• Commonly known as VPX• Defines new high-speed connectors in part to carry mapping

for popular switched sewrial fabrics including Gigabit Ethernet, PCI Express, Serial RapidIO, InfiniBand, and Aurora.

• Power envelop including a 48V and cooling methods

– Protocol mappings• VITA 46.1 Parallel VME; completed• VITA 46.2 Parallel cPCI; planned• VITA 46.3 Serial RapidIO; planned• VITA 46.4 PCI Express; planned• VITA 46.5 HyperTransport™; planned• VITA 46.x RTM (Rear Transition Module); planned


VIAT46 Standards Hierarchy


VITA 46 “AMF”

• Replace all connectors with Multi-Gig RT2 7-Row

• No switch card required– Enough pins are available to build large, rich topologies

without one

• Upside– Enough high-speed pins (192 pairs) for switch fabric and large I/O counts– Backward VME compatibility in some slots with VME on new connector– Includes a 3U version, with high-speed serial I/O and fabric– 2-level maintenance ESD ready connector system

• Downside– Not compatible with existing boards at slot level; No DINs for P1 & P2– Backward VME compatibility in some slots with VME on new connector


VPX – 3U


VPX – 6U


VPX Connector


Pin Assign


--- Defined by the VITA(VME International Trade Association) working group

--- Provides VMEbus-based systems--- Retains VME’s existing 3U and 6U form factors--- Supporting PCI mezzanine card and XMC mezzanines--- Maintaining the maximum possible compatibility with VME bus--- Growing significance of high speed serial switched fabric

interconnects such as PCI Express, RapidIO, Infiniband and 10 Gigabit Ethernet

--- Gives the large existing base of VMEbus users access to these switched fabrics

--- Provide the implementation ofmultiprocessing systems that requirethe fastest possible communicationsbetween multiple processors

--- 7-row high speed connector ratedup to 6.25Gbps

VPX


The End

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VMEBus, VXS, XMC, VPX · • VITA 41.1 VXS : Infiniband Protocol Layer • VITA 41.2 VXS : Serial...

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