Resistive switching in BiFeO3-based thin films
Transcript of Resistive switching in BiFeO3-based thin films
Resistive switching in BiFeO3-based thin films
and reconfigurable logic applications
Widerstandsschalten in BiFeO3-basierten Dünnschichten
und rekonfigurierbare Logik-Anwendungen
Von der Fakultät für Elektrotechnik und Informationstechnik
der Technische Universität Chemnitz
genehmigte
DISSERTATION
zur Erlangung des akademischen Grades
Doktor der Ingenieurwissenschaften
(Dr. -Ing.)
vorgelegt
von M. Eng. Tiangui You
geboren am 28. September 1987
in Fujian, China
eingereicht am 09. June 2016
Gutachter Prof. Dr. Prof. h.c. Oliver G. Schmidt
Prof. Dr. Xin Ou
PD Dr. Heidemarie Schmidt
Tag der Verleihung 25. October 2016
Bibliographic description
Resistive switching in BiFeO3-based thin films and reconfigurable logic applications
You, Tiangui – 149 pages, 39 figures, 4 tables, 185 references
Technische Universität Chemnitz
Faculty of Electrical Engineering and Information Technology
Dissertation (in english language), 2016
Abstract
The downscaling of transistors is assumed to come to an end within the next years, and the
semiconductor nonvolatile memories are facing the same physical downscaling challenge.
Therefore, it is necessary to consider new computing paradigms and new memory concepts.
Resistive switching devices (also referred to as memristive switches) are two-terminal
passive device, which offer a nonvolatile switching behavior by applying short bias pulses.
They have been considered as one of the most promising candidates for next generation
memory and nonvolatile logic applications. They provide the possibility to carry out the
information processing and storage simultaneously using the same resistive switching device.
This dissertation focuses on the fabrication and characterization of BiFeO3 (BFO)-based
metal-insulator-metal (MIM) devices in order to exploit the potential applications in
nonvolatile memory and nonvolatile reconfigurable logics. Electroforming-free bipolar
resistive switching was observed in MIM structures with BFO single layer thin film. The
resistive switching mechanism is understood by a model of a tunable bottom Schottky barrier.
The oxygen vacancies act as the mobile donors which can be redistributed under the writing
bias to change the bottom Schottky barrier height and consequently change the resistance of
the MIM structures. The Ti atoms diffusing from the bottom electrode act as the fixed donors
which can effectively trap and release oxygen vacancies and consequently stabilize the
resistive switching characteristics. The resistive switching behavior can be engineered by Ti
implantation of the bottom electrodes.
MIM structures with BiFeO3/Ti:BiFeO3 (BFO/BFTO) bilayer thin films show nonvolatile
resistive switching behavior in both positive and negative bias range without electroforming
process. The resistance state of BFO/BFTO bilayer structures depends not only on the writing
bias, but also on the polarity of reading bias. For reconfigurable logic applications, the
polarity of the reading bias can be used as an additional logic variable, which makes it
feasible to program and store all 16 Boolean logic functions simultaneously into the same
single cell of BFO/BFTO bilayer MIM structure in three logic cycles.
Keywords: bipolar resistive switching, BiFeO3, tunable Schottky barrier, mobile donors,
fixed donors, Ti-implantation, nonvolatile memory, reconfigurable nonvolatile logics.
Bibliographische Beschreibung
Widerstandsschalten in BiFeO3-basierten Dünnschichten und rekonfigurierbare Logik-
Anwendungen
You, Tiangui – 149 Seiten, 39 Abbidungen, 4 Tabellen, 185 Referenzen
Technische Universität Chemnitz
Fakultät für Elektrotechnik und Informationstechnik
Dissertation (in englischer Sprache), 2016
Kurzfassung
Die Herunterskalierung von Transistoren für die Informationsverarbeitung in der
Halbleiterindustrie wird in den nächsten Jahren zu einem Ende kommen. Auch die
Herunterskalierung von nichtflüchtigen Speichern für die Informationsspeicherung sieht
ähnlichen Herausforderungen entgegen. Es ist daher notwendig, neue IT-Paradigmen und neue
Speicherkonzepte zu entwickeln. Das Widerstandsschaltbauelement ist ein elektrisches passives
Bauelement, in dem ein der Widerstand mittels elektrischer Spannungspulse geändert wird.
Solche Widerstandsschaltbauelemente zählen zu den aussichtsreichsten Kandidaten für die
nächste Generation von nichtflüchtigen Speichern sowie für eine rekonfigurierbare Logik. Sie
bieten die Möglichkeit zur gleichzeitigen Informationsverarbeitung und -speicherung.
Der Fokus der vorliegenden Arbeit liegt bei der Herstellung und der Charakterisierung von
BiFeO3 (BFO)-basierenden Metal-insulator-Metall (MIM) Strukturen, um zukünftig deren
Anwendung in nichtflüchtigen Speichern und in rekonfigurierbaren Logikschaltungen zu
ermöglichen. Das Widerstandsschalten wurde in MIM-Strukturen mit einer BFO-Einzelschicht
untersucht. Ein besonderes Merkmal von BFO-basierten MIM-Strukturen ist es, dass keine
elektrische Formierung notwendig ist. Der Widerstandsschaltmechnismus wird durch das Modell
einer variierten Schottky-Barriere erklärt. Dabei dienen Sauerstoff-Vakanzen im BFO als
beweglichen Donatoren, die unter der Wirkung eines elektrischen Schreibspannungspulses
nichtflüchtig umverteilt werden und die Schottky-Barriere des Bottom-Metallkontaktes ändern.
Dabei spielen die während der Herstellung von BFO substitutionell eingebaute Ti-Donatoren in
der Nähe des Bottom-Metallkontaktes eine wesentliche Rolle. Die Ti-Donatoren fangen
Sauerstoff-Vakanzen beim Anlegen eines positiven elektrischen Schreibspannungspulses ein
oder lassen diese beim Anlegen eines negativen elektrischen Schreibspannungspules wieder frei.
Es wurde gezeigt, dass die Ti-Donatoren auch durch Ti-Implantation der Bottom-Elektrode in
das System eingebracht werden können.
MIM-Strukturen mit BiFeO3/Ti:BiFeO3 (BFO/BFTO) Zweischichten weisen substitutionell
eingebaute Ti-Donatoren sowohl nahe der Bottom-Elektrode als auch nahe der Top-Elektrode
auf. Sie zeigen nichtflüchtiges, komplementäres Widerstandsschalten mit einer komplementär
variierbaren Schottky-Barriere an der Bottom-Elektrode und an der Top-Elektrode ohne
elektrische Formierung. Der Widerstand der BFO/BFTO-MIM-Strukturen hängt nicht nur von
der Schreibspannung, sondern auch von der Polarität der Lesespannung ab. Für die
rekonfigurierbaren logischen Anwendungen kann die Polarität der Lesespannung als zusätzliche
Logikvariable verwendet werden. Damit gelingt die Programmierung und Speicherung aller 16
Booleschen Logik-Funktionen mit drei logischen Zyklen in dieselbe BFTO/BFO MIM-Struktur.
Stichworte: bipolares Widerstandsschalten, BiFeO3, veränderliche Schottky-Barriere,
beweglichen Donatoren, feste Donatoren, Ti-Implantation, nichtflüchtige Widerstandsspeicher,
rekonfigurierbare und nichtflüchtige Logikanwendungen
i
Table of Contents
List of Symbols ................................................................................................................ I
List of Abbreviations ................................................................................................... III
Chapter 1 Introduction and motivation ....................................................................... 1
Chapter 2 Fundamentals ............................................................................................... 5
2.1 Overview of nonvolatile memories......................................................................... 5
2.1.1 Flash memory ................................................................................................... 5
2.1.2 Magnetoresistive random-access-memory ....................................................... 7
2.1.3 Ferroelectric memory ....................................................................................... 8
2.1.4 Phase-change memory ..................................................................................... 9
2.1.5 Resistive switching memory .......................................................................... 10
2.2 Fundamental mechanisms of resistive switching behavior................................... 11
2.2.1 Filamentary resistive switching...................................................................... 12
2.2.2 Interface resistive switching ........................................................................... 16
2.3 Theory of Schottky barrier .................................................................................... 20
2.3.1 Electric transport across a single Schottky barrier ......................................... 20
2.3.2 Electric transport across two anti-serially connected Schottky barriers ........ 21
2.4 Applications of resistive switching ....................................................................... 23
2.4.1 Nonvolatile memory....................................................................................... 23
2.4.2 Digital logic applications ............................................................................... 24
2.4.3 Neuromorphic computing .............................................................................. 25
ii
Chapter 3 Experimental methods............................................................................... 29
3.1 BFO thin film fabrication by pulsed laser deposition (PLD) ............................... 29
3.1.1 PLD basics ..................................................................................................... 29
3.1.2 BFO ceramic target preparation .................................................................... 31
3.1.3 BFO thin film deposition by PLD ................................................................. 31
3.2 Top electrode preparation..................................................................................... 32
3.3 Electrical measurements ....................................................................................... 33
3.3.1 Current-Voltage (I-V) measurement ............................................................. 33
3.3.2 Retention and endurance measurements ....................................................... 33
3.4 Material characterization ...................................................................................... 34
3.4.1 X-ray diffraction (XRD) ................................................................................ 34
3.4.2 Transmission electron microscopy (TEM) .................................................... 35
3.4.3 Atomic force microscopy (AFM) and conductive AFM (C-AFM) ............... 36
3.4.4 Time-of-flight secondary ion mass spectrometry (TOF-SIMS) .................... 36
Chapter 4 Resistive switching in BiFeO3 thin films with a single tunable barrier 39
4.1 Device structure and fabrication .......................................................................... 40
4.2 Resistive switching characteristics ....................................................................... 41
4.2.1 I-V characteristics .......................................................................................... 41
4.2.2 Retention and endurance tests ....................................................................... 42
4.3 Resistive switching mechanism ........................................................................... 45
4.3.1 Role of fixed donors and of mobile donors ................................................... 45
4.3.2 Dynamic resistive switching .......................................................................... 48
4.4 Tunable Schottky barrier heights ......................................................................... 50
4.4.1 Schottky barrier heights in HRS .................................................................... 52
iii
4.4.2 Schottky barrier heights in LRS ..................................................................... 53
4.5 Local resistive switching ...................................................................................... 53
4.6 Conclusions ........................................................................................................... 55
Chapter 5 Engineering resistive switching by Ti implantation of bottom electrodes
........................................................................................................................................ 57
5.1 Device fabrication and material characterization ................................................. 58
5.1.1 Fabrication of Au-BFO-Pt MIM structures with different Ti fluences .......... 58
5.1.2 Ti distribution in Pt/Sapphire and surface morphology of Pt/Sapphire ......... 59
5.1.3 Ti distribution in BFO thin films and surface morphology of BFO thin films
................................................................................................................................. 60
5.2 Resistive switching characteristics ....................................................................... 61
5.2.1 I-V characteristics .......................................................................................... 61
5.2.2 Retention and endurance tests ........................................................................ 63
5.3 Dependence of Schottky barrier height on the Ti fluence .................................... 66
5.3.1 Schottky barrier heights in HRS .................................................................... 66
5.3.2 Schottky barrier heights in LRS ..................................................................... 68
5.4 Local resistive switching ...................................................................................... 69
5.5 Conclusions ........................................................................................................... 71
Chapter 6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable
barriers .......................................................................................................................... 73
6.1 Device structure and fabrication ........................................................................... 74
6.2 Resistive switching characteristics ....................................................................... 76
6.2.1 I-V characteristics .......................................................................................... 76
6.2.2 Retention and endurance tests ........................................................................ 77
6.3 Resistive switching mechanisms .......................................................................... 78
iv
6.4 Nonvolatile reconfigurable logic applications ..................................................... 82
6.4.1 Reading bias dependent resistance state ........................................................ 82
6.4.2 Sequential logic operation ............................................................................. 82
6.4.3 Reconfigurable Boolean logic operations...................................................... 84
6.5 Conclusions .......................................................................................................... 86
Chapter 7 Summary and outlook ............................................................................... 87
7.1 Summary .............................................................................................................. 87
7.2 Outlook ................................................................................................................. 89
References ..................................................................................................................... 91
Appendix A ................................................................................................................. 107
Appendix B ................................................................................................................. 109
Versicherung .............................................................................................................. 115
Theses .......................................................................................................................... 117
List of Figures ............................................................................................................. 121
List of Tables .............................................................................................................. 125
Acknowledgments ...................................................................................................... 127
Publications and presentations ................................................................................. 129
Curriculum Vitae ....................................................................................................... 133
I
List of Symbols
A* effective Richardson constant
A contact size
T temperature
φ0 zero-bias Schottky barrier height
q elementary electric charge
Rs series resistance
Rp parallel resistance
n ideality factor
kB Boltzmann constant
Meff effective electron mass
h Planck constant
φ Schottky barrier height
εs dielectric permittivity of the semiconductor
N dopant concentration
Ψs surface potential
ni intrinsic carrier concentration
ΔWg band gap
E electric field
Dt top diode
Db bottom diode
φt top Schottky barrier height
φb bottom Schottky barrier height
Ri bulk resistance
List of Symbols
II
Rb bottom resistance in LRS
φt' top Schottky barrier height in LRS
Dt' top diode in LRS
φt0 zero-bias top Schottky barrier height
φb0 zero-bias bottom Schottky barrier height
φt-HRS top Schottky barrier height in HRS
φb-HRS bottom Schottky barrier height in HRS
Ra mean arithmetic roughness
ILRS current of LRS
IHRS current of HRS
U+writing positive writing voltage
U-writing negative writing voltage
U+reading positive reading voltage
U+reading negative reading voltage
Out output
S` initial state
r reading bias
III
List of Abbreviations
CMOS complementary metal–oxide–semiconductor
MIM metal-semiconductor (or insulator)-metal
BFO BiFeO3
BFTO Ti-doped BiFeO3
IEDM International Electron Devices Meeting
MOSFET metal-oxide-semiconductor field-effect transistor
FG floating gate
MRAM magnetoresistive random-access-memory
STT-MRAM Spin Transfer Torque MRAM
FeRAM ferroelectric random-access-memory
1T-1C one transistor-one capacitor
FeFET ferroelectric field-effect transistor
PCM phase-change memory
RS resistive switching
PCMO Pr0.7Ca0.3MnO3
CC current compliance
I-V Current-Voltage
HRS high resistance state
LRS low resistance state
BLFO La-doped BiFeO3
TEM transmission electron microscopy
SEM scanning electron microscopy
XRF micro-X-ray fluorescence
List of Abbreviations
IV
RT room temperature
ET elevated temperature
SIMS secondary ion mass spectrometry
Pt/Nb:STO Pt/Nb:SrTiO3
SRO SrRuO3
RRAM resistive random-access-memory
SRAM static random-access-memory
DRAM dynamic random-access-memory
IMP material implication
BRS bipolar resistive switches
CRS complementary resistive switches
FTJ ferroelectric tunneling junction
MTJ magnetic tunnel junction
STDP spike timing dependent plasticity
XRD X-ray diffraction
AFM atomic force microscopy
PLD pulsed laser deposition
CVD chemical vapor deposition
MBE molecular beam epitaxy
ALD atomic layer deposition
EDX energy-dispersive X-ray spectroscopy
GIXRD Grazing Incidence X-ray Diffraction
𝑉𝑂∙ charged oxygen vacancies
HAADF-STEM high-angle annular dark-field scanning transmission
electron microscopy
PFE Poole-Frendel emission
SE Schottky emission
MSE modified Schottky emission
T1 terminal 1
T2 terminal 2
PLRS low resistance state in positive bias
List of Abbreviations
V
PHRS high resistance state in positive bias
NLRS low resistance state in negative bias
NHRS high resistance state in negative bias
C. HV1 first cycle of high voltage
C.HV2 second cycle of high voltage
C.LV cycle of low voltage
1
Chapter 1 Introduction and motivation
For approximately half a century, intensive down-scaling of transistors has been the most
important strategy for performance enhancement in semiconductor integrated circuit
technology (usually dubbed CMOS technology) which has arguably been the most successful
technical advance of our civilization.[1] According to Moore’s law,[2] the number of
components per integrated function (i.e. transistors per chip) doubles approximately every
18 months. However, keeping with this relentless course of miniaturization turns out to be
very challenging for the future technology node.[3, 4] The semiconductor nonvolatile
memories, such as flash memory in which the data is stored in form of electric charges within
a conductive layer (floating-gate) embedded into a gate stack of a field effect transistor, are
facing the same physical down-scaling challenge. Therefore, there is a strong demand on
new memory concepts, which will be able to overcome the scaling limitation of the
contemporary technology.
Resistive switching device is considered as one of the most promising candidates for the next
generation nonvolatile memories.[5-17] Resistive switching device consists only of a metal-
semiconductor (or insulator)-metal (MIM) sandwich stack, whose resistance can be changed
between two or more resistance states by the voltage/current applied on the two metal
electrodes and be maintained without power supply. Being used as the next generation
nonvolatile memory, resistive switching device offers the potential advantages of high
density, low power consumption, fast switching speed, and compatibility with conventional
CMOS technology. In 2008, researchers from HP laboratories[18] revealed the missing link
between the two-terminal resistive switching device and the memristor which was envisioned
by Leon O. Chua in 1971 as the fourth basic circuit element in addition to resistor, capacitor,
and inductor.[19] After that, resistive switching device is identified as memristor and the
research community has shown great interest on demonstrating exclusive solid-state
1 Introduction and motivation
2
implementations of memristor not just for the next generation of highly scalable non-volatile
memories,[16, 17] but also for reconfigurable nonvolatile logics,[20-24] neuromorphic
computing,[25-29] and hardware-based data encryption.[30-32]
Meanwhile, BiFeO3 (BFO) with rhombohedral structure belonging to R3c space group has
attracted great interest in the last decade due to the coexistence of ferroelectric and
antiferromagnetic characteristics with both high Curie temperature and Néel temperature
(approximately 653 K and 1100 K, respectively).[33-36] In addition to the potential
applications in the fields of magnetism, spintronic, photovoltaic etc., the resistive switching
behavior has been also observed in BFO-based MIM structures in recent years.[37-43] Most
of the observed resistive switching behaviors are attributed to the switching of ferroelectric
polarization or the migration of oxygen vacancies under applied electric field. However, the
ferroelectric polarization fatigue would limit the endurance property and the migration of
oxygen vacancies under low electric field with longer time constant might cause the resistive
switching degradation by the small reading bias which limits the retention time.[11]
Therefore, the mechanism of the resistive switching behavior in BFO thin films is not well
understood and the challenges still remain to achieve excellent resistive switching
performance, including long retention time, good endurance, fast switching activity, and
large storage window. The aim of this thesis is to clarify the physical mechanism underlying
the observed switching behaviors in BFO-based MIM structures which is critical for the
future device design, to engineer the resistive switching behaviors of BFO thin films by ion
implantation, and to exploit the MIM structures with BiFeO3/Ti:BiFeO3 (BFO/BFTO)
bilayer thin films for the reconfigurable nonvolatile logic applications.
The thesis is organized as follows.
In Chapter 2, a brief introduction on the different nonvolatile memory techniques is presented,
and an overview will be given concerning the fundamental theories of resistive switching.
In Chapter 3, the sample preparation process and the characterization techniques are briefly
introduced.
In Chapter 4, a nonvolatile resistive switching in metal-BFO-metal MIM structures is shown,
and a resistive switching model based on the tunable Schottky barrier height is proposed to
explain the observed resistive switching behaviors.
1 Introduction and motivation
3
In Chapter 5, the engineering of the resistive switching in BFO-based MIM structures by Ti
implantation on the bottom electrodes is introduced.
In Chapter 6, the resistive switching characteristics of the MIM structures with BFO/BFTO
bilayer thin films are studied, and the application for the reconfigurable nonvolatile logics is
introduced.
In Chapter 7, the overall conclusions are summarized and several suggestions for the future
work are proposed.
5
Chapter 2 Fundamentals
2.1 Overview of nonvolatile memories
2.1.1 Flash memory
So far, the semiconductor storage market has been dominated by the flash memory which
is one of the most commonly used semiconductor devices thanks to its high density, low
cost, fast write/read speed, and nonvolatility.[44] The flash memory was invented by Dr.
Fujio Masuoka in 1980, and the invention was announced at the IEEE 1984 international
Electron Devices Meeting (IEDM) in San Francisco.[45] The flash memory is
constructed using floating-gate metal-oxide-semiconductor field-effect transistor
(MOSFET) as shown in Figure 2.1, in which an additional floating gate (FG) is buried
underneath the control gate and electrically isolated from the control gate and the
semiconductor.[46] FG may be made of conductive materials like poly-silicon or can also
be non-conductive. The writing/erasing process is accomplished by injecting electrons
Source
n+ n+Drain
Floating Gate
Control Gate
p-Substrate
Thin oxide layer
Tunnel oxide
Figure 2.1: Schematic sketch of a floating-gate MOSFET. The gate on top is called the
control gate, and the bottom one is called the floating gate. These two gates
are separated from each other by a thin oxide layer.
2.1 Overview of nonvolatile memories
6
into FG or removing electrons from FG through the tunnel oxide, while readout is
realized by sensing the current flowing between the source and drain. Since the FG is
surrounded by highly resistive materials, the charge stored inside the FG can maintain
for long time. Therefore, it is used as the basic functional element in nonvolatile flash
memories.
According to how the cells are organized in the matrix, flash memory can be categorized
into NOR flash and NAND flash.[47] The early flash memories were based on NOR type,
which provided full addressing and allowed random access to the memory unit. For
writing operation in NOR type flash memories, the drain-source voltage has to be high
enough to activate the hot-carriers in the channel and overcome the barrier height
between the Si and SiO2. Therefore, the channel length cannot be reduced unlimitedly
due to the risk of breakdown by the high drain-source voltage. To overcome this problem
and to decrease the memory size, the NAND type flash memory was developed by
Toshiba. NAND flash uses Fowler-Nordheim tunneling for erasing and programming.
NAND flash allows for a high storage capacity and supports a fast writing/erasing rate
and therefore has been widely used for storage applications including USB drives,
memory cards, and solid state drives.[48] Compared with NAND flash, NOR Flash
usually gives a faster readout rate but at the expense of storage density. Hence, NOR
Flash is often used where fast code execution is required such as in the BIOS of personal
computers and handheld devices including cellphones and PDAs.[49]
However, it should be noted that although the performance of flash memory has been
improved significantly during the last decade with the aid of some innovative scaling
technologies, it will inevitably approach its fundamental physical limits. First, the tunnel
oxide layer inside flash memory needs to be thicker than 8 nm in order to eliminate
possible electron leakage, thus eroding the scaling margin.[50] Second, the gate coupling
ratio must be maintained at a value greater than 0.6 so as to control the conductive
channel and prevent gate electron injection.[51] This can be achieved by wrapping the
control gate around the floating gate to geometrically increase the gate coupling ratio.
Obviously, adequate space is unavailable to contain such a wrapping structure when the
downscaling process continues. Furthermore, a relatively long distance between two
2 Fundamentals
7
adjacent cells inside Flash memory is required to suppress the crosstalk effect that the
electrons stored in one cell would start to have on adjacent cells, adversely affecting the
performance of scaled devices.[52] Owing to the aforementioned drawbacks, the state-
of-the-art NOR and NAND devices are restricted to 45 nm[52] node and 20 nm[50] node
sizes, respectively.
2.1.2 Magnetoresistive random-access-memory
Magnetoresistive effect is defined as that the electrical resistance of a material can be
changed by the applied external magnetic field.[53] Magnetoresistive random-access-
memory (MRAM) is a memory technology based on the magnetoresistive effect, which
consists of two magnetic storage elements, one with a fixed magnetic polarity and another
with a switchable polarity.[54, 55] These magnetic elements are positioned on top of each
other but separated by a thin insulating tunnel barrier as shown in Figure 2.2.[55]
Technically, it works with the state of the cell, which is sensed by measuring the electrical
resistance while passing a current through the cell. Because of the magnetic tunnel effect,
if both magnetic moments are parallel to each other, then the electrons will be able to
tunnel and the cell is in the low resistance “On” state. While, if the magnetic moments
are antiparallel, the cell resistance will be high and the cell is in “Off” state.[55]
The writing and erasing processes were achieved by the overlapping magnetic fields
generated by current pulses in orthogonal wires crossing over the cell.[55] The main
limiting factors of MRAM are the large cell size (due to the programming mechanism),
the small Ion/Ioff ratio (in the order of 30%), the high programming currents and the
programming disturbs to neighboring cells generated by parasitic magnetic fields.[56]
Figure 2.2: Schematic structure of MRAM cell.
Ferromagnetic fixed Layer
Ferromagnetic free Layer
Tunnel Barriere- e- e- e- e- e- e-
Parallel stateLow resistance: On
Antiparallel stateHigh resistance: Off
2.1 Overview of nonvolatile memories
8
Spin Transfer Torque MRAM (STT-MRAM) was developed to exert the base platform
established by the existing MRAM to enable a scalable nonvolatile memory solution for
advanced process nodes.[57, 58] However some issues are still to be solved, like the
overall low Ion/Ioff ratio, the small voltage window between programming and breakdown
voltages, problems of stability of magnetic polarization. And the main drawback of
MRAM is that the switching of magnetization requires a significantly large current
density, which induces high power consumption.
2.1.3 Ferroelectric memory
It is well known that the polarization of the ferroelectric materials can be toggled between
two distinct states by applying an external electric field. Therefore, these two opposite
polarization states can be used to represent binary bits “0” and “1”,[59] thus resulting in
the advent of the ferroelectric random access memory (FeRAM).[60-62] As shown in
Figure 2.3 (a), the basic FeRAM cell is consisting of one ferroelectric capacitor and one
access transistor, resulting in a one transistor-one capacitor (1T-1C) memory cell (Figure
2.3 (c)). To detect the stored memory state, a voltage pulse is applied to the capacitor
during reading and a transient current response is simultaneously sensed. Depending on
(a) (b)
(c) (d)
Figure 2.3: Schematic device configurations of two types of ferroelectric memory, (a)
FeRAM and (b) FeFET, and the corresponding circuit diagrams, (c) FeRAM
and (d) FeFET.
Ferroelectric
n+ n+
p-Substrate
Word lineBit line Ferroelectric
n+ n+
p-Substrate
Word lineBit line
Ferroelectric
Word line
Bit
lin
e Ferroelectric
Word line
Bit
lin
e
2 Fundamentals
9
the initial polarization state the ferroelectric polarization either is reversed or remains
unchanged, resulting in different value of the transient current response. Since the
polarization state is changed during the readout operation, i.e., the readout is destructive,
it must be rewritten each time after reading.[63] This imposes the requirement of a high
endurance resistivity on the ferroelectric material.
To achieve a non-destructive readout, the ferroelectric field-effect transistor (FeFET) has
been proposed, where the insulating oxide layer is replaced by a ferroelectric layer as
shown in Figure 2.3 (b) and (d).[64] The conductivity of the transistor channel is
modulated by the polarization charge of the ferroelectric layer, which can be controlled
by a voltage applied to the gate electrode. A positive gate voltage results in a positive
polarization charge at the ferroelectric-semiconductor interface, attracting electrons and
increasing the channel conductivity. The ferroelectric polarization can be reversed by a
negative gate voltage, which decreases the conductivity of the channel due to the negative
polarization charge at the ferroelectric-semiconductor interface.[63]
However, the main drawback of ferroelectric memories until now has been their poor
scalability, since the signal is proportional to the area of the capacitor and inversely
proportional to thickness, which is limited in scaling by the interaction of ferroelectric
material with the electrodes.[56] Moreover there are process integration problems, like
the sensitivity to Hydrogen contamination in the back-end process, the need to use special
materials for electrodes like Platinum, Iridium and Rhodium.[56] Additionally, due to
the high deposition temperature of most ferroelectric materials, the integration of
ferroelectric layer into microelectronics becomes difficult, and conductive oxide bottom
electrode has to be used to ensure the endurance, which raises the product costs.
2.1.4 Phase-change memory
Phase-change memory (PCM) is a type of nonvolatile memory based on a class of
materials called chalcogenide glasses that can exist in two different phase states (e.g.,
crystalline and amorphous).[65] As shown in Figure 2.4, a PCM cell consists of top and
bottom electrodes with the phase change layer and the heater resistor material embedded
in between. The most commonly used phase-change materials contain at least one
2.1 Overview of nonvolatile memories
10
element from group VI in the periodic table. Particularly, the most promising are
Ge2Sb2Te5 and Sb2Te3 alloys, and these materials doped with impurities such as nitrogen
or oxygen have also been studied with the aim of improving operation speed or thermal
stability. [66-69]
The structure of the phase-change material can be changed rapidly back and forth
between amorphous and crystalline on a microscopic scale above the heater. The material
has low electrical resistance in the crystalline or ordered phase and high electrical
resistance in the amorphous or disordered phase. This allows electrical currents to be
switched between “On” and “Off”, representing digital high and low states.[56] The main
advantages of PCM are fast switching times (10~100 ns), low operation voltages (1~2
V), high endurance with 109 cycles, the capability of multi-level data storage and
relatively uncomplicated integration into the CMOS process flow.[70, 71] However, the
main obstacles arise from the requirement of high current density during the writing of a
memory state. It limits the scaling of the access device, and thus the entire memory
cell.[72] Moreover, high current densities can cause a deterioration of the endurance
characteristics. Other matters of concern are the thermal cross-talk between the cells at
high storage densities, the read disturb and the retention degradation caused by the
structural relaxation.[73]
2.1.5 Resistive switching memory
Resistive switching (RS) memory is a two terminal device where the switching medium
is sandwiched between top and bottom electrodes to form a MIM capacitor structure[5]
as shown in Figure 2.5. The resistance of the switching medium can be switched between
Figure 2.4: Schematic structure of phase-change memory.
Bottom electrode
Top electrode
Phase change material
InsulatorHeater
Programmable region
2 Fundamentals
11
different resistance states by the electrical signal (current or voltage) applied on the top
and bottom electrodes.[5]
The RS memory has some advantages as compared to the previously introduced memory
technologies, the most obvious one being its simple structure.[74, 75] RS memory is
fabricated with a two-terminal MIM capacitor structure, which is suitable for large
scalable architectures, e.g., crossbar arrays. The reading operation detects the resistance
in RS memory instead of charge in flash memory,[76] making the readout easier and
simplifying the readout circuit. The RS MIM structure can be directly fabricated onto
silicon enabling stacking and achieving high memory density. In this work, we focus on
the resistive switching behavior of BFO-based MIM capacitor structure, and the
fundamental of resistive switching will be introduced in the following.
2.2 Fundamental mechanisms of resistive switching behavior
Resistive switching behavior has been widely reported in various materials, such
Pr0.7Ca0.3MnO3 (PCMO),[77, 78] SrTiO3,[79, 80] BiFeO3,[39, 41-43] TiO2,[11, 81]
NiO,[82, 83] and HfO2.[84, 85] While, the observed resistive switching behaviors vary
depending on the materials. According to the polarities of the set and reset voltages in
the I-V characteristics, resistive switching can be categorized into two types, i.e., unipolar
resistive switching and bipolar resistive switching[17] as shown in Figure 2.6. Switching
from “Off” state to “On” state is called the set process, while switching from “On” state
to “Off” state is called the reset process. And a current compliance (CC) is usually needed
during the switching process to prevent the device from a permanent breakdown. In
Figure 2.5: Schematic structure of RS memory cell.
2.2 Fundamental mechanisms of resistive switching behavior
12
unipolar resistive switching, the set and reset voltages have the same polarity but different
amplitudes (Figure 2.6 (a)). However, the set and reset are triggered by different voltage
polarities in bipolar resistive switching (Figure 2.6(b)).
Resistive switching can also be classified concerning the geometrical location of the
resistive switching events, including filamentary and interface resistive switching.[76]
We categorize the resistive switching into these two main classes in this chapter. Each of
them can be sub-divided by different physical mechanisms and shows unipolar or bipolar
switching, which will be introduced in the following.
2.2.1 Filamentary resistive switching
In filamentary resistive switching, a pretreatment process, called “electroforming”, is
normally necessary in order to activate the resistive switching by creating the conductive
filaments in the insulating matrix. The MIM capacitor structure is reset from the low
resistance state (LRS) to the high resistance state (HRS) by rupturing the conductive
filaments, and set to LRS by building up those filaments. The filaments extend from one
electrode to the other one, acting as “bridges” for charge transport throughout the
insulating matrix. Due to the different mechanisms of the filament formation, both
bipolar and unipolar resistive switching are possible. The main concern in filamentary
resistive switching lies on the question how the conductive filaments are formed.
Cu
rre
nt
Voltage
Reset
Set
Set
Reset
On
OffOff
CC
CC
On
Cu
rre
nt
Voltage
Set
Reset
On
Off
CC
Figure 2.6: (a) I-V characteristics of unipolar resistive switching. The set and reset
processes take place in the same voltage polarity. (b) I-V characteristics of
bipolar resistive switching. The set and reset processes take place in the
different voltage polarities. Adapted from Ref. [17].
(a) (b)
2 Fundamentals
13
Currently, metal cation migration or oxygen vacancy migration is generally accepted to
explain the formation of filaments.
(1) Metal cation migration
One of the representatives of metal-cation-migration-induced resistive switching is Ag-
photodoped amorphous As2S3, which was reported by Hirose et al. in 1976.[86] By using
Ag-doped As2S3 as the insulating layer sandwiched between Mo top electrode and Ag
bottom electrode, bipolar resistive switching was observed in the MIM capacitor
structure as shown in Figure 2.7 (a). Ag-doped As2S3 is a kind of solid electrolyte, in
which the transport occurs via the migration of Ag cations. As shown in Figure 2.7 (b)
and (c), Ag cations move towards the Mo electrode driven by the external voltage, and
the set process occur when both electrodes (Mo and Ag) are bridged by Ag filaments
which originates as the result of Ag photodoping. By turning the voltage into the opposite
polarity, the Ag atoms near the Mo electrode dissolve into cations, annihilating the Ag
filaments and switch off the system. Recently, metal cation migration was also observed
in Al/Cu/GeSe/W structure, in which Cu filaments were formed throughout the GeSe
layer between the Cu and W electrodes.[87] The structure also shows a bipolar resistive
switching behavior.
Metal filaments are not only observed in solid electrolytes, but also in oxides. A stable
bipolar resistive switching was reported in La-doped BiFeO3 (BLFO) thin films
sandwiched by Ag and Pt, or Cu and Pt,[38] which was attributed to the formation of
Figure 2.7: (a) I-V characteristics of Al/Cu/GeSe/W structures. Schematic views of the
filament formation and dissolution in LRS (b) and HRS (c). Adapted from
Ref. [87].
(a) (b) (c)
LRS HRS
LRS
2.2 Fundamental mechanisms of resistive switching behavior
14
nanoscale metal filaments due to the diffusion of top electrode (Ag or Cu) driven by the
external voltage. Note that the electrode materials plays an important role in the resistive
switching induced by the metal cation migration. Li et al. [38] also reported that the
resistive switching is unstable in the MIM capacitor structures of Al/BLFO/Pt or
Au/BLFO/Pt, due to the formation of a thin AlOx layer at top interface, or the large ionic
radius of Au which makes the Au ion diffusion difficult in the BLFO layer.
(b) Oxygen vacancy migration
In addition to the formation of metal filaments, other defects in the oxides, e.g., oxygen
vacancies, tend to cluster and generally form conductive filamentary shapes under an
external electric field.[79, 88] Oxygen vacancies are inevitably introduced during the
oxide thin film deposition or oxide single crystal growth, and considerably change the
electrical properties of the oxides. Resistive switching is strongly coupled with the
concentration and distribution of oxygen vacancies. Driven by external voltage,
conductive filaments induced by the migration of oxygen vacancies can be formed. Those
filaments can be electrically built-up/cut-off, consequently switching on/off the system.
The movement of metal cations inside a material can be relatively easily observed using
direct microscopic imaging techniques like transmission electron microscopy (TEM) or
scanning electron microscopy (SEM). However, in comparison to the metal cations, the
observation of oxygen vacancy migration inside a bulk oxide is much more difficult due
to the smaller atomic number of oxygen.[89]
A direct observation of filaments in oxides containing oxygen vacancies has been
reported in a Pt/Cr:SrTiO3/Pt MIM capacitor structure which shows bipolar resistive
switching behavior as indicated in Figure 2.8 (a).[90] By combining the laterally resolved
micro-X-ray fluorescence (XRF) spectroscopy and thermal imaging, the underlying
mechanism of the resistive switching in Cr:SrTiO3 thin films was revealed. Figure 2.8 (b)
shows an infrared thermal image of the memory cell which was collected when applying
an electrical current of +5 mA with a bias voltage of ca. 30 V. The temperature
distribution of the memory cell can be reflected by the false-color image. The temperature
increases laterally and is highest at the anode. This indicates a conductive path between
the anode and cathode. The corresponding distribution of oxygen vacancies was
2 Fundamentals
15
investigated by the XRF mapping as shown in Figure 2.8 (c). It is clear that the oxygen
vacancies distribute along the conductive path revealed by Figure 2.8 (b). This is strong
evidence that the resistive switching in Cr:SrTiO3 thin films originates from the
formation/rupture of the conductive filaments due to the oxygen vacancy migration.[90]
So far, it has been shown that the key point of filamentary resistive switching focuses on
the formation of conductive filaments in the insulating layer caused by the migration of
the metal cations or oxygen vacancies. However, the electroforming process is usually
required before the observation of resistive switching, which is used to initialize the
conductive filaments. Thereafter, the build-up/cut-off only occurs at the terminal point
of the filament near the top or bottom electrode, while the rest part of the filament inside
the insulating layer remains unchanged during the switching.[91] Although the
filamentary resistive switching only occurs near the interface, it is essentially different
from the “interface resistive switching” that will be introduced in the following. It is
worthy to note that a physical and/or chemical reaction often takes place within the MIM
capacitor structure during the filament electroforming, build-up, and cut-off processes.
For example, the filamentary resistive switching behaviors are normally associated with
Figure 2.8: (a) I-V characteristics of the conditioned Cr:SrTiO3 memory cell at ambient
temperatures. (b) Infrared thermal image of the memory cell with a current of
+5 mA at an applied voltage of ca. 30 V. In the color scale, blue and red
represent room temperature (RT) and elevated temperature (ET), respectively.
The absolute temperature calibration cannot be obtained as the local
temperature for a hot spot cannot be resolved by the microscope. (c) Cr X-
ray-fluorescence map taken at 6004.3 eV for maximum contrast at the Cr pre-
edge region. The color scale represents the concentration of oxygen vacancies
(Vo•). Adapted from Ref. [90].
RT
ET
(b)
No Vo•
Vo•
Anode
Cathode
(c) (a) LRS
HRS HRS
LRS
LRS LRS
2.2 Fundamental mechanisms of resistive switching behavior
16
the redox reaction between the insulating layer and the electrodes,[92-96] or the local
Joule heating along the filaments.[97-101] This could induce some irreversible
destruction on the electrode as shown in Figure 2.9,[102] which is difficult to control.
From the point of view for the practical applications, it is essential to eliminate the
deformation of the electrodes.
2.2.2 Interface resistive switching
Another type of resistive switching is attributed to the interface effect, in which the
resistance change is related to the modulation of the interface property. The barrier height
or the depletion thickness at the metal/oxide interface is manipulated by the external
voltage, which consequently modulates the interface transport properties. This type of
resistive switching is dependent on the voltage polarity, therefore, only bipolar resistive
switching is available. Although the modification of barrier potential has already been
widely accepted as the origin for resistive switching in some metal/oxide structures, the
underlying physical mechanism that causes the nonvolatile switching is still under debate.
The most popular models include ion migration, charge trapping, and polarization
switching, which are discussed in the following.
(a) Ion migration
It is generally believed that oxygen vacancies act as the mobile donors in oxides,[103,
104] and the acceptors in p-type oxides can be compensated by oxygen vacancies.[104]
Figure 2.9: SEM images showing the morphological change as a results of the
electroforming process of a Pt(10 nm)/TiO2(27 nm)/Pt(10 nm) cell. Adapted
from Ref. [102].
2 Fundamentals
17
The mobile oxygen vacancy donors can be repelled from or attracted toward the
metal/oxide interface by an external electric field. Therefore, local charge carrier
concentration near the interface can be changed, which modulates the interface transport
property and induces resistive switching. This type of resistive switching is polarity
dependent. The voltage polarities for set and reset processes are different in p-type and
n-type conducting oxides as shown in Figure 2.10. For example, in n-type TiO2, the
accumulation of oxygen vacancies at the interface increases the donor concentration and
lowers the barrier height, and consequently the MIM capacitor structure is set to LRS.
However, the barrier height is recovered by the reduction of the oxygen vacancies at the
interface, and the MIM capacitor structure is reset to HRS. While in p-type oxide, such
as PCMO, an opposite process is needed.[76]
The migration of oxygen vacancies has been introduced in Chapter 2.2.1. However, the
interface resistive switching induced by oxygen vacancy migration is essentially different
from the filamentary resistive switching related to the oxygen vacancy migration. The
interface resistive switching is only related to the interface barrier height or depletion
thickness, but the bulk insulating layer does not contribute to the resistance change.
Usually, the insulating materials for the interface resistive switching are leaky, so that
the resistance state can be solely controlled by the interface property. However, the
transport of the filamentary switching is dominated by local filaments throughout the
Figure 2.10: Accumulation of oxygen vacancies near the top metal/oxide interface
raises/lowers the Schottky barrier height, and switches the structure to
high/low resistance state for p-type/n-type oxides. Removing oxygen
vacancies from the top metal/oxide interface lowers/raises the Schottky
barrier height, and switches the structure to low/high resistance state for p-
type/n-type oxides. Adapted from Ref. [76].
2.2 Fundamental mechanisms of resistive switching behavior
18
insulating layer. Although the filament build-up/cut-off only takes place near the
interface once the filaments are formed, the filaments distribute throughout the whole
insulating layer, and contribute to the transport characteristics.
(b) Charge trapping/detrapping
A few models have suggested that the Schottky barrier height can also be modulated by
the charge trapping/detrapping, especially for the defect-rich oxides.[105-107] By
changing the voltage polarity, charges are trapped or detrapped at the metal/oxide
interface, which modifies the Schottky barrier height, and switches the MIM capacitor
structure to different resistance states. Figure 2.11 shows a schematic diagram of
Schottky junction formed at Pt/Nb:SrTiO3 (Pt/Nb:STO) interface due to the oxygen
vacancies.[107] When a positive writing bias is applied to the Pt electrode, electrons
escape from the defect sites and the charged defects remain at the Schottky junction,
which narrows the Schottky barrier width and the device is consequently set to LRS.
When a negative writing bias is applied to the Pt electrode, the electrons are injected into
Figure 2.11: Schematic diagram of Pt/Nb:STO Schottky junction. Left: with a positive
applied voltage, electrons escape from the defect sites, so many defects
remain near the Schottky junction, which results in narrowing of the
Schottky barrier width and induces HRS-to-LRS switching. With a negative
applied voltage, electrons are trapped at the defect sites, so many defects are
neutralized near the Schottky junction, which results in recovery of the
original width of the Schottky barrier and induces LRS-to-HRS switching.
Open circles mean positively charged oxygen vacancies, and filled circles
mean neutral oxygen vacancies. Adapted from Ref. [107].
2 Fundamentals
19
the oxides and trapped at the defect sites to neutralize the oxygen vacancies, making the
Schottky barrier wider. As a result, the tunneling current decreases and the device is reset
to HRS. Therefore, the set and reset processes occur when positive and negative writing
biases are applied to the Pt electrode, respectively.
Fujii el al.[108] proposed another electron trapping/detrapping model without affecting
the Schottky barrier, in which the tunneling pathways are expected to be controlled by
the electron trapping/detrapping at the trap sites. Applying a negative writing bias,
electrons are injected into the oxides and captured in the trap sites, which leads to the
closure of resonant tunneling pathways. As a result, electrons cannot resonantly tunnel
through the Schottky barrier and the device is reset to HRS. Applying a positive writing
bias, the trapped electrons are extracted from the trap sites, and the trap sites become
available as pathways for resonant tunneling through the Schottky barrier, so the device
is set to LRS.
(c) Polarization switching
Finally, there is another mechanism that is more particular than the above ones, which is
related to the polarization switching in ferroelectric materials. Polarization switching
changes the type of surface polarization charges of ferroelectric layer, which modifies
the barrier potential at the metal/ferroelectric interfaces. Since the surface polarization is
spontaneous and nonvolatile, nonvolatile resistive switching can be realized. Up to now,
Figure 2.12: Schematic energy band diagrams of Pt/BFO/SRO capacitor-like structure
illustrating the variations in Schottky barriers from back-to-back diodes at
virgin (a) to a reverse diode at polarized up (b) and a forward diode at
polarized down (c). Adapted from Ref. [37].
(a) (b) (c)
(a) (b) (c)
2.2 Fundamental mechanisms of resistive switching behavior
20
BFO has been proved to be a good candidate for the polarization switching related
resistive switching thanks to the large remanent polarization.[37, 40, 43, 109, 110] As
shown in Figure 2.12, the Schottky barriers are expected to be formed at both top Pt/BFO
and bottom BFO/SRO (SRO: SrRuO3) interfaces in the assumption of no contribution
from the as-grown polarization. When BFO is polarized up, negative polarization charge
formed at bottom BFO/SRO interface, in which the built-in potential increases and the
depletion region becomes wide accompanied with upward band bending and an enhanced
Schottky barrier. While, the reverse phenomena occur at the top Pt/BFO interface, where
the band bending goes down and an Ohmic contact forms at top interface. Therefore, in
the polarized up case, the enhanced Schottky barrier at bottom interface plays a dominant
role in the conduction, so that the capacitor like structure works as a reverse diode and it
is in HRS with a positive reading bias. Similarly, the polarized down capacitor like
structure works as a forward diode and it is in LRS for a positive reading bias. Note that
the mechanism introduced here is different from that for the FeRAM and FeFET, which
was introduced in Chapter 2.1.3. The polarization switching related resistive switching
takes the advantage of the resistance change tailed by the bounded polarization charge,
wherein the read-out is non-destructive. In the FeRAM the polarization charge is directly
detected and the read-out process destroys the stored data. The FeFET is based on the
three-terminal FET structure, in which the channel conduction is tuned by the
polarization state of the ferroelectric material in the gate, and the state is read out by
sensing the current between the drain and source.
2.3 Theory of Schottky barrier
2.3.1 Electric transport across a single Schottky barrier
As introduced in Chapter 2.2.2, the interface resistive switching could be attributed to
the modulation of the Schottky barriers at the metal/oxide interfaces by the applied
external electric fields. The Schottky barrier is formed due to the different work functions
of the metal layer and the oxide layer, which reveals a current rectification. In forward
bias the Schottky barrier is conducting and in revise bias the current is suppressed. The
2 Fundamentals
21
electric transport of a single Schottky barrier can be described by the Shockley
equation[111] as follows:
𝐼 = 𝐴𝐴∗𝑇2 ∙ exp (−𝑞𝜑0
𝑘𝐵𝑇) (exp (
𝑞(𝑉−𝐼𝑅𝑠)
𝑛𝑘𝐵𝑇) − 1) +
(𝑉−𝐼𝑅𝑠)
𝑅𝑝 (2.1)
where
𝐴∗ =4𝜋𝑞𝑚𝑒𝑓𝑓𝑘2
ℎ3 (2.2)
is the effective Richardson constant, A is the contact size, T is the temperature, φ0 is the
zero-bias Schottky barrier height, q is the elementary electric charge, Rs is the series
resistance, Rp is the parallel resistance, n is the ideality factor, kB is the Boltzmann
constant, meff is the effective electron mass and h is the Planck constant. The Schottky
barrier height φ is decreased for charge carrier emission due to image-force barrier
lowering in the presence of an electric field, which is called Schottky effect.
Mathematically, the barrier lowering can be expressed as[112]
𝜑 = 𝜑0 − ∆𝜑=𝜑0 − [𝑞3𝑁|ψ𝑠|
8𝜋2𝜀𝑠3 ]
1
4 (2.3)
Here, εs is the dielectric permittivity of the semiconductor, N is the dopant concentration,
ψs is the surface potential which is given by:
ψ𝑠 = 𝜑0 − 𝜑𝑛 − 𝑉 ≈ 𝜑0 − (𝑞∆𝑊𝑔
2−
𝑘𝐵𝑇
𝑞ln (
𝑁
𝑛𝑖)) − 𝑉 (2.4)
where ni is the intrinsic carrier concentration and ∆Wg is the band gap of the
semiconductor. According to Eq. (2.3), the barrier lowering is proportional to 𝑁1
4 .
Therefore, the electric current can be modulated by controlling the doping concentration
at the interface, which is accompanied by a resistance change. The Schottky barrier
height can be fitted from the I-V curve of a single Schottky barrier by using Eq. (2.1).
2.3.2 Electric transport across two anti-serially connected Schottky barriers
If two Schottky barriers are anti-serially connected in a MIM structure, in general the
MIM structure is initially highly insulating, as at least one barrier is polarized in reverse
direction. The reversed current can be governed by Poole-Frenkel emission[113],
2.3 Theory of Schottky barrier
22
Schottky emission[113] or modified Schottky emission[114] mechanisms. The reverse
current considering Poole-Frenkel emission is given by[113]
𝐼 ∝ 𝐸 exp (−𝑞
𝑘𝐵𝑇(𝜑 − √
𝑞𝐸
𝜋𝜀𝑠)) (2.5)
Whereas in the case of Schottky emission, it is given by[113]
𝐼 ∝ 𝑇2 exp (−𝑞
2𝑘𝐵𝑇(𝜑 − √
𝑞𝐸
𝜋𝜀𝑠)) (2.6)
Simmons showed that Eq. (2.6) is applicable to insulators only if the electronic mean-
free path in the insulator is equal to or larger than the thickness of the insulator. For
insulators in which the electronic mean-free path is less than the insulator thickness, Eq.
(2.6) is modified and written as[114]
𝐼 ∝ 𝑇3
2 𝐸 exp (−𝑞
𝑘𝐵𝑇(𝜑 − √
𝑞𝐸
4𝜋𝜀𝑠)) (2.7)
Here, I is the reverse current, E is the applied electric field.
Therefore, if Poole-Frenkel emission dominates the reverse current, the plot of ln(I/E) vs.
E1/2 should be linear. Similarly, the linear plots of ln(I/T2) vs. E1/2 and ln(I/ET3/2) vs. E1/2
indicate the Schottky emission and the modified Schottky emission contribute the reverse
current, respectively. The emission coefficient can be expressed as follows[113]
𝑆 =𝑞
𝑛𝑘𝐵𝑇√
𝑞
𝜋𝜀𝑠 (2.8)
where n=1 for Poole-Frenkel emission and n=2 for both Schottky emission and modified
Schottky emission. To distinguish which mechanism the carrier transport is dominated
by, the emission coefficient can be calculated using Eq. (2.8), and compared with the
coefficients obtained by the experimental curve fitting for Poole-Frenkel emission,
Schottky emission, and modified Schottky emission at different temperature.
The Schottky barrier height can be extrapolated by the temperature dependent I-V
characteristics. If the reverse current is dominated by Poole-Frenkel emission, the
apparent potential barrier height for a constant voltage (electric field) can be estimated
from the slope of the representation of ln(I)~1/T according to Eq. (2.5). Similarly,
2 Fundamentals
23
according to Eq. (2.6) and (2.7), the apparent potential barrier height can be estimated
from the representation of ln(I/T2)~1/T and ln(I/T3/2)~1/T for the case of Schottky
emission and modified Schottky emission, respectively.
2.4 Applications of resistive switching
2.4.1 Nonvolatile memory
The most straightforward application of the resistive switching device is in the
nonvolatile memories, known as resistive random access memory (RRAM). RRAM has
several advantages for next-generation memory. First, the simple two-terminal sandwich
capacitor-like geometry of a RRAM cell makes the device highly scalable in a crossbar
array, and enables the 3-dimensional integration capability. Second, the multilevel
resistive switching allows the multi-bit memory, and the resistance states are stable
without external power supply, so the operational energy for RRAM can be quite small.
Third, different resistance states can be switched with external electric pulses, so
rendering its operation is simple and easy. Fourth, the resistance value of each state can
be easily read by applying a very small voltage without disturbing the original state,
which allows non-destructive reading. Finally, as resistive switching behavior has been
Table 2.1: Comparison of different memory technologies including static RAM (SRAM),
dynamic RAM (DRAM), NAND flash, STT-MRAM, FeRAM, PCM, and
RRAM. Data from HP public sources (Jan. 2015) and International Technology
Roadmap for Semiconductors (http://www.itrs.net/).
Feature SRAM DRAM NAND flash STT-MRAM FeRAM PCM RRAM
Feature size (nm) 45 36 16 65 180 45 <5
Cell size (F2) 140 6 4 20 22 4 <4
Read time (ns) 0.2 2 25000 35 40 20~70 <10
Write time (ns) 0.1~0.3 10~50 100000 13~95 65 50~500 20~30
Retention as long as
voltage applied <sec. ~10 yr >10 yr >10 yr >10 yr >10 yr
Endurance (cycles) 1016 >1017 105 1012 1014 109 >1012
Energy per bit (pJ) 0.0005 0.004 101~104 0.1~1 6 2~100 0.0001
2.4 Applications of resistive switching
24
observed in numerous materials, it should be easier to find appropriate resistive switching
materials that are compatible with the current CMOS technologies. Due to these
advantages, RRAM has been considered as one of the most promising candidates for the
next generation memories, and good operating performance for a single cell unit has
already been achieved as shown in Table 2.1. The crossbar-based architecture of the
RRAM is highly scalable and shows the potential with an ultra-high storage density.[115]
For example, RRAM with the feature sizes of 10 nm and 3 nm yields possible storage
densities of 250 Gb/cm2 and 2.5 Tb/cm2, respectively.[116] The 32 Gb RRAM chip
implemented by Sandisk and Toshiba in 24 nm technology consumed 1.3 cm2 in area,
having a density of 24.5 Gb/cm2. [117]
2.4.2 Digital logic applications
The conventional von-Neumann architecture, which physically separates processing and
memory operations, is limited in so much as the processor cannot execute a program
faster than instructions and data can be fetched from and returned to memory, leading to
the well-known von-Neumann bottleneck.[118] An alternative computing architecture in
which processing and storage are carried out simultaneously and at the same physical
location could offer very significant performance benefits and overcome the von-
Neumann bottleneck.[119] In addition to the nonvolatile memory application, resistive
switching device is also very promising for the digital logic applications, which provides
the possibility to carry out the information processing and storage simultaneously and at
the same resistive switching device.[20, 21] This is known as beyond von-Neumann
computing.[21, 120, 121] Borghetti et al. [20] demonstrated that the resistive switching
devices can execute material implication (IMP), which is a fundamental Boolean logic
as shown in Figure 2.13. With appropriately chosen voltage biases (VCOND and VSET) and
a value of load resistance (RG), the state of device P in the circuit in Figure 5 (a) would
change based on the original states of the devices P and Q, while the state of device Q
will not be disturbed. Linn et al.[21] proposed a sequential logic solution to realize the
14 of the 16 Boolean logic functions (except XOR and XNOR) with a single bipolar
resistive switches (BRS) or complementary resistive switches (CRS).[122] In this thesis,
2 Fundamentals
25
a BFO/BFTO bilayer structure is developed for implementing all 16 Boolean logic
function with a single device, which will be introduced in Chapter 6.
2.4.3 Neuromorphic computing
Although much progress has been achieved in digital microprocessor, the mammalian
brains bring much more efficiency than conventional Boolean machines for many
computational tasks such as pattern recognition and classification, which is encouraging
enough to investigate brain-inspired computational networks. As one of the building
blocks in neuromorphic network, the synapse emulation has been developed using
Figure 2.13: Illustration of the material implication logic (IMP) operation. (a) Equivalent
circuit with two resistive switching devices, (b) the truth table, and (c)
corresponding experimental data. The blue and red curves in panel (c) show
the voltages applied and the absolute value of the currents read at devices P
and Q before and after the IMP voltage pulses. The measured low and high
current values reproduce the IMP truth table. Adapted from Ref. [20].
2.4 Applications of resistive switching
26
different types of nonvolatile memory technologies over the past few years, such as PCM,
ferroelectric tunneling junction (FTJs), magnetic tunnel junction (MTJ), and resistive
switches.[28, 123-125] Particularly, the two terminal resistive switching device is the
leading candidate among them due to its excellent scalability, fast switching speed and
low power consumption.
Jo et al.[26] built up resistive switching device to emulate synaptic function for the first
time. As schematically shown in Figure 2.14 (a), the resistive switching device is
constructed with a layered structure including a co-sputtered Ag and Si active layer with
a properly designed gradient of Ag/Si ratio that leads to the formation of a Ag-rich (high
conductivity) region and a Ag-poor (low conductivity) region. This helps to eliminate the
forming process of the cell. The position of a conduction front between the Ag-rich and
Ag-poor regions can be changed by consecutive potentiating or depressing pulses. Thus
the conductance of the device can be adjusted gradually (Figure 2.14 (b)). More
importantly, the most essential synaptic modification rule of competitive Hebbian
learning,[126] spike timing dependent plasticity (STDP), can also be achieved by this
device (Figure 2.14 (c)). The STDP function has also been realized in BFO-based
resistive switching device in 2012.[127]. It has been studied that the change in synaptic
weight strongly depends on the spike timing of presynaptic spikes and postsynaptic
Figure 2.14: (a) Schematic illustration of the concept of using resistive switching device
as synapses between neurons. The insets show the schematics of the two-
terminal device geometry and the layered structure of the resistive switching
device. (b) I-V characteristic of Ag/Si resistive switching device. The inset
shows the normalized Ag front position w during positive DC sweeps. (c)
STDP behaviors recorded from Ag/Si resistive switching device. Adapted
from Ref. [26].
(a) (b) (c)
2 Fundamentals
27
spikes. Based on this knowledge, the STDP realization by using the short and simplified
single pairing potentiating and depressing spike sequence was developed in 2015.[128]
29
Chapter 3 Experimental methods
In this chapter, the experimental methods and techniques are introduced: firstly, the
detailed fabrication process of a BFO-based resistive switching device including the BFO
thin film deposition and the top electrode preparation; secondly, the electrical
measurement setups including the current-voltage (I-V), retention, and endurance
measurements; and lastly, the material characterization methods including X-ray
diffraction (XRD), transmission electron microscopy (TEM), atomic force microscopy
(AFM), and time-of-flight secondary ion mass spectrometry (TOF-SIMS).
3.1 BFO thin film fabrication by pulsed laser deposition (PLD)
3.1.1 PLD basics
PLD has been widely used for thin film deposition, especially for oxide thin films. A
schematic of a PLD system is shown in Figure 3.1. With a certain incident angle, short
and intense excimer laser pulses are focused on a ceramic target, which has a similar
composition as the desired thin film. The laser ablates the surface of the target, and
instantly evaporates the target materials. As a result, a plume is generated near the surface
of the target, and extends along the normal direction of the target surface. Due to the high
energy of laser, the evaporated species gain high kinetic energy and transport inside the
plume region toward the substrate, which is placed opposite to the target. To obtain a
high-quality thin film, the target-substrate distance needs to be optimized. Generally, the
substrate should be placed near the top edge of the plume.
3.1 BFO thin film fabrication by pulsed laser deposition (PLD)
30
In comparison to other thin film deposition techniques, e.g. chemical vapor deposition
(CVD), molecular beam epitaxy (MBE), atomic layer deposition (ALD) or magnetron
sputtering, the main advantages of PLD are listed as follows:
(1) Conceptually simple: a laser beam vaporizes a target surface, producing a thin film
with the same stoichiometry as the ceramic target.
(2) Versatile: thin film deposition by PLD is not limited to specific material, many
materials can be deposited, including insulators, semiconductors, metals, and polymers.
Both ceramic, metallic and single crystal targets are applicable.
(3) Scalable: the compound thin films with complex compositions can be simply
deposited using PLD, it is possible for complex oxides to move toward volume
production. In addition, multilayer structures with controlled thickness can be easily
realized if the PLD is built up by a multi-target system.
(4) Controllable: the laser energy and repetition rate can be well controlled, and the
deposition rate of thin films can be precisely tuned, which is essential for the thin film
properties in many cases.
(5) Cost-effective: one laser can serve in many PLD chambers.
(6) Fast: high quality samples can be grown reliably in minutes or hours.
Figure 3.1: Schematic of a PLD system.
Vacuum system
Vacuum chamber
Substrate
Heater
Laser plume Target
Target spinning
LaserLaser window
3 Experimental methods
31
3.1.2 BFO ceramic target preparation
For the PLD deposition of BFO thin films, a BFO ceramic target is firstly prepared by a
conventional solid-state reaction method. Bi2O3 and Fe2O3 powder are mixed with a ratio
of 1.1:1. To compensate the evaporation of Bi element during the target sintering, excess
Bi2O3 powder is used. The mixed powder is ball-milled for 6 hours, and sintered at 750 °C
for 6 hours. After sintering, a powder with the BFO phase is formed, and the powder is
etched by 5% HNO3 solution to eliminate the impurity phases. Finally, the BFO powder
is pressed into a disk and sintered at 840 °C for 2 hours. Then the pure BFO ceramic can
be obtained.
For the Ti doped BFO (BFTO) thin film, Ti ions are used to substitute some of the Fe
ions in BFO due to the closed ionic radius of Ti4+ and Fe3+ (0.68 Å and 0.65 Å,
respectively).[129] A BFTO ceramic target is prepared by using the Bi2O3, Fe2O3, and
TiO2 powder with a Bi:Fe:Ti ratio of 1.1:0.99:0.01, and the other process stays the same
as the BFO target preparation.
3.1.3 BFO thin film deposition by PLD
The BFO and BFTO thin films are deposited with a PLD system equipped by a KrF
excimer laser, which outputs 30 nm long laser pulses with a wavelength of 248 nm. The
substrate is mounted onto a sample holder, and the target-substrate distance is 60 mm.
The substrate is heated up with a ramping rate of 20 °C/min. In this thesis, all the
substrates have a Pt or Pt/Ti layer that serves as the bottom electrode for the BFO or
BFTO thin films, and the substrate temperature is 650 °C unless noted otherwise. Before
deposition, the PLD chamber is evacuated to a background pressure of ~6E-4 mbar, and
then the oxygen is introduced with an oxygen partial pressure of 1.3E-2 mbar. The laser
is calibrated to the desired energy for each deposition. The pulse laser energy is ~300 mJ,
which is partially lost when the laser is focused by the quartz lens. The laser energy on
the surface of the target is ~156 mJ, which produces a nominal laser energy density of
~2.6 J/cm2 with a laser spot size of 0.06 cm2. The deposition rate and thickness of thin
films are controlled by the repetition rate and number of the laser pulses, respectively.
3.1 BFO thin film fabrication by pulsed laser deposition (PLD)
32
The repetition rate is 10 Hz and the laser pulse number will be specified in the following
chapters.
To compensate the oxygen vacancies generated during the thin film deposition, oxygen
is introduced into the PLD chamber with nominal oxygen pressure of 200 mbar after the
thin film deposition. The substrate is cooled down to 390 °C with a cooling rate of
5 °C/min, and a post-annealing process is applied with annealing time of 60 min. Finally,
the substrate is naturally cooled down to room temperature.
3.2 Top electrode preparation
For electrical characterization, the top electrodes are prepared in order to construct a
metal-BFO (or BFTO)-metal MIM capacitor structure as shown in Figure 3.2. If not
specified, Au is chosen as the top electrode material, which is deposited by DC magneto-
sputtering at room temperature with a metal shadow mask. The circular top electrode size
is 0.045 mm2 unless noted otherwise. The sputtering is carried out with a power of 100
W in an Ar ambient (2.6 Pa). The sputtering time is 180 seconds, which deposits Au layer
with a thickness of ~100 nm.
Figure 3.2: Schematic sketch of the fabricated MIM capacitor structure and the electric measurement configuration.
Substrate
TiPt
BFO/BFTO
Au
Keithley
Sourcemeter
3 Experimental methods
33
3.3 Electrical measurements
3.3.1 Current-Voltage (I-V) measurement
The electrical measurements were carried out by a two-probe configuration with a
Keithley 2400 Sourcemeter unless noted otherwise as shown in Figure 3.2. The bias
voltage is applied between the Au top electrode and the Pt bottom electrode. The
maximum magnitude of the bias applied on the Au top electrode is 8 V unless noted, and
the Pt bottom electrode is grounded. The I-V measurements are conducted by applying a
DC triangular voltage sweep and recording the current through the sourcemeter. Figure
3.3 shows a schematic representation of the DC triangular voltage sweep.
3.3.2 Retention and endurance measurements
The stability of the resistive switching is characterized by the retention and endurance
tests. The retention tests are carried out by first applying a set or reset voltage to switch
the MIM capacitor structure to LRS or HRS at room temperature, and followed by
detecting the resistance state with a small reading bias very 2 min at room temperature
or at elevated temperature. Figure 3.4 (a) shows a schematic representation of the voltage
pulses for the retention tests. The monitored reading current would indicate whether the
resistance state undergoes degradation or it is stable. The endurance tests are carried out
Figure 3.3: Schematic representation of the DC triangular voltage sweep.
-8
0
8
Volta
ge
(V
)
Time
3.3 Electrical measurements
34
at room temperature by repeating the set/read/reset/read process as shown in Figure 3.4
(b). The reading current is recorded and the variation of the resistance state can be
analyzed.
3.4 Material characterization
3.4.1 X-ray diffraction (XRD)
XRD is a non-destructive method used for identifying the crystal structure of a crystalline
materials, as well as the crystal symmetry, lattice parameters, lattice strain, qualitative
and quantitative phase composition and preferred orientation of grains in polycrystalline
materials.[130] X-ray is a form of electromagnetic radiation, with a wavelength between
0.01 to 10 nm and energies in the range from 100 eV to 100 keV. XRD is based on
constructive interference of monochromatic X-rays and a crystalline sample. These X-
rays are generated by a cathode ray tube, filtered to produce monochromatic radiation,
collimated to concentrate, and directed toward the sample. The interaction of the incident
rays with the sample produces constructive interference (and a diffracted ray) when
conditions satisfy Bragg’s Law (nλ=2d sin θ). These diffracted X-rays are then detected,
processed and counted. The most useful configuration for thein film analysis is grazing
incidence XRD (GIXRD).[131] The GIXRD scheme is schematically shown in Figure
3.5, in which the incidence angle α between the incident X-ray beam (K0) and the sample
surface is kept constant, while the detector is rotated on a goniometer circle and the
Figure 3.4: Schematic representation of the voltage pulses for the (a) retention and (b)
endurance tests.
(a) (b)
Time
Voltage
Set
or
Rese
t
Re
ad
Set R
ead
Re
set
Re
ad
Time
Voltage
3 Experimental methods
35
intensity of the diffracted X-ray beam (Kf) is recorded for different 2θ angles. In this
configuration the penetration depths of the X-rays remain closer to the thin film thickness
than that in the symmetric geometries, such as the Bragg-Brentano configuration. As a
result, the interaction of the X-rays with the thin film material is maximized while the
possible interference of the substrate is minimized. Therefore, more detailed information
about the thin film can be acquired. In this thesis, the GIXRD measurement was
characterized by a Bruker D8 Advance diffractometer with parallel beam geometry using
Cu Kα radiation at a fixed angle of incidence of 7°. The indexing of the reflections was
carried out using the PDF-4+2010 database of the International Center for Diffraction
Data.
3.4.2 Transmission electron microscopy (TEM)
TEM is a microscopy technique enabling to study the sample’s microstructure with sub-
nanometer resolution. Utilization of electrons with significantly smaller de Broglie
wavelength (λ < 0.05 Å) instead of the visible light (λ in the range 3900 – 7000 Å)
provides a considerably higher resolution capability of TEM in comparison with the light
microscopy. By using TEM, both images and diffraction patterns of the specific specimen
area can be obtained. These are formed by electrons transiting through a thin specimen.
Due to interaction of transmitted electrons with the matter of the specimen, they contain
information about its microstructure. Three main principles of the contrast formation in
Figure 3.5: Schematic representation of the diffractometer setup used in GIXRD
measurement. Q is the scattering plane, K0 is the incident vector, Kf is the
diffracted vector and α is the incidence angle.
Substrate
Detector
α
2θ
K0
QKf
3.4 Material characterization
36
TEM images are distinguished[132], namely, mass-thickness contrast, diffraction
contrast and phase contrast. The latter is utilized by a high-resolution TEM to image
material structure on the atomic scale. The samples studied with TEM should be thin
enough (less than 100 nm) in order to obtain sufficient intensity of the transmitted
electron beam. Therefore, specific specimen preparation from the bulk samples prior to
actual TEM analyses is required. Mechanical thinning, electrochemical thinning or ion
milling can be exploit for this purpose. In this thesis, the scanning TEM and the energy-
dispersive X-ray spectroscopy (EDX) measurements were performed with an image-
corrected FEI Titan 80–300 microscope and a JEOL JEM 2200FS double Cs-corrected
scanning transmission electron microscope.
3.4.3 Atomic force microscopy (AFM) and conductive AFM (C-AFM)
AFM gives the 3D information of a surface on the nanometer scale including the
roughness, depth, and morphology. The working principle is designed on the basis of
measuring forces between the tip and sample.[133] The tip is mounted at the end of a
flexible cantilever. The force is measured by the spring constant of the cantilever and the
tip-sample distance, and described by Hook’s law. If the tip is quite far away from the
sample surface, forces hardly exist. When the tip comes closer to the surface, the
attractive Van der Waals force is dominant. Even closer or nearly in contact with the
surface, the repulsive Van der Waals force will dominate in the system. C-AFM is a
conventional AFM operating in contact mode utilizing a conductive cantilever and tip.
The voltage is applied between the conductive AFM tip and the sample to collect the
desired electrical information. C-AFM measures the resulting current signal completely
independent from the topography which is simultaneously recorded via the cantilever
deflection. C-AFM could provide the in situ direct observation of resistive switching with
nanometric resolution.[82, 134, 135] In this thesis, AFM and C-AFM measurements were
carried out with an Agilent Technologies 5420 scanning probe microscope.
3.4.4 Time-of-flight secondary ion mass spectrometry (TOF-SIMS)
Secondary ion mass spectrometry (SIMS) is a mass spectrometry technique, in which
high energetic primary ions impinge on the sample surface, resulting in a cloud of
3 Experimental methods
37
molecules, clusters, and atoms that is partly ionized. Typically, a quadrupole or a double
focusing sector field spectrometer separates the ions according to their mass to charge
ratio. TOF-SIMS is an acronym for the combination of the SIMS technique with time of
flight mass analysis (TOF), which takes advantage of the differing drift times of
secondary ions that are accelerated in the same electric field. They are produced by a
short primary ion pulse and then pass an electrostatic extraction field that accelerates
them. All equally charged ions gain the same kinetic energy. Ions having the same
ionization state but different masses will therefore obtain distinctive drift velocities after
acceleration. Consequently, the drift times required to reach the detector are related with
the mass to charge ratio of the ions. TOF-SIMS provides elemental, chemical state, and
molecular information from surfaces of solid materials. By combining TOF-SIMS
measurements with ion milling (sputtering) to characterize a thin film structure, the depth
distribution information can be obtained.[136, 137] In this thesis, TOF-SIMS
measurements were carried out by an IONTOF TOF-SIMS 5 equipment with an O2
sputtering beam (2000 eV) and a Bi analysis beam (25000 eV).
39
Chapter 4 Resistive switching in BiFeO3 thin films
with a single tunable barrier
In recent years, BFO has attracted considerable attention as a new type of resistive
switching material,[37, 39-43, 81, 138-144] thanks to its fascinating physical properties,
e.g., the coexistence of ferroelectric and antiferromagnetic characteristics with both high
Curie temperature and Néel temperature (approximately 653 K and 1100 K, respectively)[33-
36], photovoltaic effect[109, 145] et al., which offers the potential to develop radical new
concepts for resistive switching devices. However, different types of resistive switching
behavior, e.g., bipolar and unipolar resistive switching,[37, 39-43, 81, 138-144, 146, 147]
were reported in BFO based MIM capacitor structures, and the resistive switching
mechanism of BFO thin films is still controversial as introduced in Chapters 1 and 2.
In this chapter, the BFO thin films on Pt/Ti/Sapphire or Pt/Ti/SiO2/Si substrates are
fabricated and show excellent bipolar resistive switching performances such as
electroforming free, multi-level states, long retention time, and stable endurance, in
which the Ti diffusion from the bottom electrodes during BFO thin film deposition plays
an important role. A model based on tunable Schottky barrier heights is proposed to
explain the bipolar resistive switching in BFO thin films, in which the ionized oxygen
vacancies (𝑉𝑂∙ ) and diffused Ti act as mobile and fixed donors, respectively. The mobile
𝑉𝑂∙ donors are redistributed by a writing bias which changes the Schottky barrier height
at the bottom interface, and the fixed Ti donors can trap the mobile 𝑉𝑂∙ donors after the
writing process to stabilize the resistive switching.
4.1 Device structure and fabrication
40
4.1 Device structure and fabrication
As introduced in Chapters 3.1 and 3.2, BFO thin films were deposited by PLD on
Pt/Ti/Sapphire, Pt/Sapphire, and Pt/Ti/SiO2/Si substrates with the same PLD conditions.
The nominal laser energy density, laser repetition rate, oxygen ambient pressure, and
growth temperature are 2.6 J/cm2, 10 Hz, 0.013 mbar, and 650 °C, respectively. After the
BFO deposition, the BFO thin films were in situ annealed at 390 °C with a nominal
oxygen ambient pressure of 200 mbar for 60 min. The nominal thickness of BFO thin
films is 600 nm. Following the PLD process, circular Au top contacts with an area of
0.045 mm2 and a thickness of ~100 nm were fabricated by DC magnetron sputtering at
room temperature using a metal shadow mask. The schematic sketch of the as-prepared
samples is displayed in the inset of Figure 4.1 (a).
Figure 4.1 (b) shows the typical Grazing Incidence X-ray Diffraction (GIXRD) pattern of
the BFO thin films deposited by PLD. The GIXRD experiments with a fixed angle of
incidence of 7° were carried out to avoid complete overload of the signal by the
substrate.[148] All the peaks correspond to the rhombohedral structure of BFO with R3c
space group (JCPDS no.: 71-2494),[149] which indicates that polycrystalline perovskite
BFO film has been deposited by PLD.
20 40 60 80
(13
4)
(30
0)
(11
6)
(02
4)
(20
2)
(00
6)
(11
0)
(10
4)
2 (degree)
Inte
nsity (
a.u
.) (01
2)(a)
(b)
Figure 4.1: (a) Schematic sketch and (b) typical Grazing Incidence X-ray Diffraction
(GIXRD) pattern of the as-prepared samples.
Substrate
Pt/Ti
BFO
Au
Keithley
Sourcemeter
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
41
4.2 Resistive switching characteristics
4.2.1 I-V characteristics
The I-V measurements were carried out with a Keithley 2400 sourcemeter. The
schematic sketch of the electrical measurement configuration is shown in Figure 4.1 (a),
in which the bias voltage is applied between Au top electrode and Pt bottom electrode.
The Pt bottom electrode is grounded and the forward bias is defined as a positive bias
applied to the Au top contact. Figure 4.2 shows the I-V characteristics obtained from two
pristine cells of the Au-BFO-Pt/Ti/Sapphire, Au-BFO-Pt/Ti/SiO2/Si, and Au-BFO-
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
650 oC
(2)
(1)
(4)
(3)
(4)
(3)
(2)
LRS
on Pt/Ti/SiO2/Si
|Curr
ent| (
A)
Voltage (V)
0 V +8 V -8 V 0 V
0 V -8 V +8 V 0 V
HRS
(1)
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
on Pt/Ti/Sapphire
0 V +8 V -8 V 0 V
0 V -8 V +8 V 0 V
|Curr
ent| (
A)
Voltage (V)
650 oC
(2)
(4)
(1)(3)
HRS
(1)
(3)
LRS
(4)(2)
-10 0 101E-10
1E-8
1E-6
1E-4
550 oC on Pt/Ti/SiO
2/Si
|Cu
rre
nt| (
A)
Voltage (V)
0 V +10 V -10 V 0 V
0 V -10 V +10 V 0 V
(2)
(4)
(1)
(3)
(1)
(3)
(4)(2)
(d)
-15 -10 -5 0 5 10 151E-10
1E-8
1E-6
1E-4
on Pt/Sapphire
|Curr
ent| (
A)
Voltage (V)
0 V +15 V -15 V 0 V
0 V -15 V +15 V 0 V
(2)
(4)
(1)
(3)
(1)
(3)
(4)(2)
650 oC
(b)
Figure 4.2: I-V characteristics with two different voltage sweeping sequences
measured at two pristine cells of the BFO thin films deposited on (a)
Pt/Ti/Sapphire, (b) Pt/Ti/SiO2/Si, and (c) Pt/Sapphire substrates at 650 oC, and on (d) Pt/Ti/SiO2/Si substrate at 550 oC. The numbers (1)–(4)
and the arrows indicate the voltage sweeping sequences and the voltage
sweeping directions, respectively.
(c)
(a)
4.2 Resistive switching characteristics
42
Pt/Sapphire MIM structures by applying a DC triangular voltage sweep as shown in
Figure 3.3 with the voltage sequences of 0 V +8 V -8 V 0 V (black curve) and
0 V -8 V +8 V 0 V (red curve). Both Au-BFO-Pt/Ti/Sapphire and Au-BFO-
Pt/Ti/SiO2/Si MIM structures show typical bipolar resistive switching behavior, in which
a distinct current hysteresis is observed at the positive bias range. The pristine MIM
structures exhibit HRS, and LRS is set by a positive bias (+8 V), while the MIM
structures are reset to HRS by a negative bias (-8 V). Note that the I-V characteristics do
not depend on the bias sweeping direction as there is no significant difference between
the black and red curves in Figure 4.2, which suggests that the as-prepared BFO-based
MIM structures show bipolar resistive switching behavior without an electroforming
process. However, there is no distinct resistive switching behavior in Au-BFO-
Pt/Sapphire MIM structure even when the voltage bias is increased to ±15 V as shown in
Figure 4.2 (c). It indicates that the Ti diffusion into BFO layer during the PLD deposition
process plays a critical role on the resistive switching of BFO-based MIM structures[41,
141] which will be discussed later.
4.2.2 Retention and endurance tests
To check the nonvolatility and reliability of the resistive switching in Au-BFO-
Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures with electroforming-free
bipolar resistive switching, the pulse retention and endurance tests were performed. As
introduced in Chapter 3.3, the retention tests were carried out by first applying a writing
bias pulse of +8 V or -8 V for 100 ms at room temperature to switch the MIM structures
to LRS and HRS, respectively, and followed by detecting the resistance state with a small
reading bias pulse of +2 V every 2 minutes at room temperature, 328K and 358 K. The
retention characteristics of Au-BFO-Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM
structures are pretty similar as shown in Figure 4.3 (a) and (c), respectively. For both
MIM structures, the HRS is quite stable at room temperature, while the HRS at 328 K
and 358 K initially exhibits decreasing resistance (increase in the detected current) and
becomes stable within 24 hours. However, a degradation exists in all LRS tests. In both
Au-BFO-Pt/Ti /Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures, a stable LRS was
obtained after around 5 hours at room temperature and at 328 K, but the LRS at 358 K
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
43
did not stabilize until around 40 hours later. After 24 hours, the resistance ratio RHRS/RLRS
was around 100 at each test temperature. As indicated by the dashed lines in Figure 4.3
(a) and (c), the resistance ratio RHRS/RLRS of both MIM structures can be well kept after
10 years at room temperature, 328 K, and 358 K.
The endurance tests were carried out at room temperature by repeating the
set/read/reset/read process for more than 3×104 times. As shown in Figure 4.3 (b), highly
stable LRS and HRS reading currents with the resistance ratio RHRS/RLRS more than 300
were recorded in Au-BFO-Pt/Ti/Sapphire MIM structure. The statistical data is given by
100
102
104
106
108
1E-10
1E-8
1E-6
358 K
358 K
328 K
328 K
RT
LRS
@ +2 Von Pt/TiSiO2/Si
Cu
rre
nt
(A)
Time (s)
10
ye
ars
HRSRT
1 10 100 1000 100001E-10
1E-8
1E-6
RT
Cu
rre
nt
(A)
Cycles
on Pt/Ti/SiO2/Si
HRS
LRS
6 7 8 9 101E+00
1E+02
1E+04
Count
Log (R)
LRS HRS
(c) (d)
Figure 4.3: Retention test results at room temperature (RT), 328 and 358 K for the (a)
Au-BFO-Pt/Ti/Sapphire and (c) Au-BFO-Pt/Ti/SiO2/Si MIM structures. The
extrapolated 10-year HRS/LRS retention time can be expressed by the
dashed lines. Endurance test result at RT for the (b) Au-BFO-Pt/Ti/Sapphire
and (d) Au-BFO-Pt/Ti/SiO2/Si MIM structures. The inset in (b) and (d)
indicates a statistics histograms of LRS/HRS. The LRS/HRS are set/reset by
a writing bias of +8 V/−8 V with pulse length of 100 ms. The resistance states
were read at +2 V.
100
102
104
106
108
1E-10
1E-8
1E-6
Cu
rre
nt
(A)
Time (s)
10
yea
rs358 K
328 K
RT
358 K328 K
RTHRS
LRS
on Pt/Ti/Sapphire @ +2 V
1 10 100 1000 100001E-10
1E-8
1E-6
on Pt/Ti/Sapphire
HRS
LRS
RT
Cu
rre
nt
(A)
Cycles
6 7 8 9 101E+00
1E+02
1E+04HRS
Co
un
t
Log (R)
LRS
(a) (b)
4.2 Resistive switching characteristics
44
the inset in Figure 4.3 (b), which indicates a narrow distribution of the resistance values
in LRS and in HRS. The relative fluctuations (standard deviation divided by mean value)
of LRS and HRS are 1.89% and 0.56%, respectively. However, as shown in Figure 4.3
(d) the LRS and HRS reading currents in Au-BFO-Pt/Ti/SiO2/Si MIM structure are
fluctuant during the endurance test with the relative fluctuations of 12.27% and 19.42%
for LRS and HRS, respectively. It is expected that the different endurance characteristics
of Au-BFO-Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures depends on the
roughness of the BFO-Pt interface. Figure 4.4 shows the high-angle annular dark-field
scanning transmission electron microscopy (HAADF-STEM) images and the energy-
dispersive X-ray spectroscopy (EDX) mapping images of Ti and Pt in Au-BFO-
Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures. The Pt/Ti interface in Au-
BFO-Pt/Ti/Sapphire MIM structure is not visible in the cross-section HAADF-STEM
image due to the serious interdiffusion of Pt and Ti as indicated by the EDX mapping
images in Figure 4.4 (a). It clear that the Ti diffuses into the BFO layer in both Au-BFO-
(b)
Figure 4.4: Cross-section HAADF-STEM images and the EDX mapping images of Ti
(blue) and Pt (red) in (a) Au-BFO-Pt/Ti/Sapphire and (b) Au-BFO-
Pt/Ti/SiO2/Si MIM structures.
(a)
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
45
Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures revealed by the EDX mapping
images. The cross-section HAADF-STEM image shows a rough BFO-Pt bottom
interface in Au-BFO-Pt/Ti/Sapphire MIM structure, however, the BFO-Pt bottom
interfaces in Au-BFO-Pt/Ti/SiO2/Si MIM structure is smooth. With a rough BFO-Pt
bottom interface, the local electric field is enhanced around the protrusions and directs
the drift of charged oxygen vacancies (𝑉𝑂∙ ),[150, 151] which contributes to the resistive
switching in the MIM structures as discussed later. The randomness of the paths for the
𝑉𝑂∙ drift is reduced as in the case of ZnO resistive switching devices with Ag-
nanoclusters.[150] Therefore, Au-BFO-Pt/Ti/Sapphire MIM structure with a rough BFO-
Pt bottom interface possess much more stable endurance test results than Au-BFO-
Pt/Ti/SiO2/Si MIM structure with a smooth BFO-Pt bottom interface. This suggests that
the development of structured electrodes can solve the issue of non-uniformity for future
ReRAM.[150, 151] The retention and endurance test results indicate that the
electroforming-free bipolar resistive switching in both Au-BFO-Pt/Ti/Sapphire and Au-
BFO-Pt/Ti/SiO2/Si MIM structures is nonvolatile and stable.
4.3 Resistive switching mechanism
4.3.1 Role of fixed donors and of mobile donors
As a gradually changing current is observed from the I-V characteristics of both Au-
BFO-Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures, the mechanism of the
resistive switching is interface-mediated instead of filament-related.[20, 81] As shown in
Figure 4.4 (a), the mechanism of the bipolar resistive switching observed in BFO thin
films can be explained by the tunable Schottky barrier at the BFO-Pt bottom interface by
the drift of 𝑉𝑂∙ under applied large electric fields during the writing step. Note that the
bipolar resistive switching may also be attributed to the electron trapping/detrapping or
by the ferroelectric switching as introduced in Chapter 2. However, these two
possibilities can be excluded by the fact that the bipolar resistive switching from the
electron trapping/detrapping mechanisms result in intrinsically low retention time[152,
153], and by the fact that the obvious ferroelectricity was not observed from the samples
4.3 Resistive switching mechanism
46
and the resistive switching can be tuned by the magnitude and length of the writing bias
pulse which will be discussed later. As BFO can be considered as a n-type semiconductor
due to the naturally formed 𝑉𝑂∙ , the Schottky-like barriers are formed at both top Au-BFO
and bottom BFO-Pt interfaces.[154] The Ti diffusion from the Ti layer in the substrate
causes the formation of a TiO2 layer on the Pt surface,[155] which can be incorporated
into the BFO film as in the case of PbZrTiO3.[156] The Ti in BFO thin film was observed
by the EDX mapping images as shown in Figure 4.4. There is no distinct resistive
switching behavior in MIM structure of Au-BFO-Pt/Sapphire without a Ti layer in the
bottom electrode (Figure 4.2 (c)) and in MIM structure of Au-BFO-Pt/Ti/SiO2/Si with
lower BFO deposition temperature of 550 oC in which Ti cannot effectively diffuse into
BFO layer. This suggests that the Ti diffusing from the Pt/Ti bottom electrode plays a
critical role on the resistive switching behaviors of the BFO-based MIM structures.
Compared to the 𝑉𝑂∙ , it is more difficult for Ti4+ to migrate in perovskite materials due to
the larger ionic radius of Ti4+ (0.68 nm) and the larger Ti migration energy.[157]
Therefore, under moderate bias pulses only 𝑉𝑂∙ acts as mobile donor while Ti4+ acts as
fixed donor in BFO. In pristine state, the donors evenly distribute between Au top
electrode and Pt/Ti bottom electrode, and most of the fixed Ti4+ donors are accumulated
near the BFO-Pt bottom interface due to a Ti diffusion from the Pt/Ti bottom electrode
into BFO during the BFO deposition at elevated temperature.
As shown in Figure 4.5, the equivalent circuit of HRS is a head-to-head rectifier which
consists of two anti-serially connected diodes (Dt and Db) due to the Schottky-like contact
(φt and φb) at both top (t) and bottom (b) interfaces and one resistor Ri denoting the bulk
resistance of the BFO thin film. When a positive reading bias is applied, the current is
blocked by the reversed bottom diode Db, thus the MIM structure is in HRS. Due to the
negative writing bias, the mobile 𝑉𝑂∙ donors drift towards the Au-BFO top interface,
which sets up a small concentration gradient of donors. The resulting small concentration
gradient of donors is stable at room temperature, while some of the mobile 𝑉𝑂∙ donors
may diffuse towards the BFO-Pt bottom interface at 328 K and at 358 K due to the
increasing diffusivity of the mobile 𝑉𝑂∙ donors with increasing temperature and the low
potential barrier as indicated in the left side of Figure 4.5. This diffusion mildly decreases
the Schottky barrier height at the bottom interface (φb) and further increases the detected
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
47
current. Therefore, a degradation of HRS was observed in the retention tests at 328 K
and at 358 K as shown in Figure 4.3 (a) and (c). After applying a positive writing bias,
most of the mobile 𝑉𝑂∙ donors drift towards the BFO-Pt bottom interface. The distribution
of mobile 𝑉𝑂∙ donors is tunable by the defects in perovskite materials.[158-160] As shown
in Figure 4.5, close to the bottom interface several large potential barriers are formed on
the atomic scale by the fixed Ti4+ donors. Once being drifted into the deep potential wells
most of the mobile 𝑉𝑂∙ donors are trapped and can only leave the potential wells within
an external electric field. The Schottky-like barrier at the BFO-Pt bottom interface is
reduced resulting in an Ohmic contact (Rb) while the Schottky-like barrier at the Au-BFO
top interface (φt') is increased due to the accumulation of donors at the bottom
interface.[11, 161] By applying a positive reading bias, the diode Dt' is forward biased
and the MIM structures exhibit LRS. The increasing resistance of LRS observed in the
retention tests may be due to the weak diffusion of mobile 𝑉𝑂∙ donors away from the BFO-
Pt bottom interface which slightly increases the Schottky-like barrier at the bottom
Figure 4.5: Schematic presentation of the distribution of mobile 𝑉𝑂∙ (black circles) and
fixed Ti4+ (orange circles) donors in the BFO thin film for HRS and LRS. The
band diagrams of the Schottky barriers and the corresponding equivalent
circuits are indicated in the left side of the schematic for each resistance state.
Schematics of the potential profile for mobile 𝑉𝑂∙ donors are shown in the right
side of the schematic for each resistance state.
LRS
Dt
Rb
Ri
+
+ +
+ + +
+ + +
Potential
+
+
++
++
++
+
Ti4+ Fe3+ Vo
Positive
writing
Negative
writing
HRS
+
+
+
+
+
+
++
+
Dt
Db
Ri
Potential
+
+
++
+
++
+ +
Au BFO Pt/Ti
4.3 Resistive switching mechanism
48
interface as there is a strong 𝑉𝑂∙ concentration gradient between top and bottom contact.
After applying a negative writing bias, the mobile 𝑉𝑂∙ donors are released from the deep
potential wells and drift towards the top electrode. Thus the Schottky-like barrier at the
BFO-Pt bottom interface is recovered and the MIM structure is reset to HRS.
4.3.2 Dynamic resistive switching
It is difficult to directly and nondestructively characterize the physical changes
responsible for the resistive switching, because the active regions of the devices are
extremely small and buried under a metal contact.[11] In order to obtain further insight
into the modification of the interface barrier by the redistribution of mobile 𝑉𝑂∙ donors,
the I-V curves in the small voltage range from -2 V to +2 V were measured from the Au-
BFO-Pt/Sapphire MIM structure after applying a writing bias pulse with different
magnitude and length. Note that the Au-BFO-Pt/Sapphire MIM structure was fully reset
to HRS by -8 V for 100 ms before applying every single positive writing bias pulse (+8
V, +7 V, +6 V, +4 V), while it was fully set to LRS by +8 V for 100 ms before applying
every single negative writing bias pulse (-8 V, -7 V, -6 V, -4 V). Figure 4.6 (a) shows the
I-V curves measured after applying a writing bias with the same pulse length of 100 ms
but with different amplitudes on Au-BFO-Pt/Ti/Sapphire MIM structure. It is clear that
the current is small in both positive and negative voltage ranges when the MIM structure
was fully reset to HRS (-8 V, 100 ms) which suggests a head-to-head rectifier behavior.
While, a forward rectification characteristic is observed when the MIM structure is fully
set to LRS (+8 V, 100 ms) which suggests a forward rectifier behavior. This is in
agreement with the equivalent circuits presented in Figure 4.5. Under the assumption that
the drift length of mobile 𝑉𝑂∙ is 600 nm with the writing bias of +8 V for 100 ms, the
mobility of 𝑉𝑂∙ is calculated to be 4.5×10-9 cm2/V•sec (drift length L=v×t, drift velocity
v=μ×E, where t, µ and E denote the drift time, mobility and electric field, respectively),
which is in the agreement with the reported mobility of 𝑉𝑂∙ in the range between 10-10 and
10-8 cm2/V•sec in perovskite-type materials.[162-164] The behavior of the MIM structure
as a forward rectifier or as a head-to-head rectifier becomes less pronounced with
decreasing the magnitude of the writing bias. As the drift length of mobile 𝑉𝑂∙ decreases
with decreasing electric fields, the MIM structure cannot be fully set/reset to LRS/HRS
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
49
with a small writing bias. With the writing bias pulse length of 100 ms, the MIM structure
cannot be set to LRS by the writing bias amplitude smaller than +7 V, however, the MIM
structure cannot be reset to HRS by the writing bias amplitude below -4 V. The writing
bias pulse length also influences the drift length of 𝑉𝑂∙ . Figure 4.6 (b) shows the I-V curves
measured after applying writing bias pulses of different length with the magnitude of 8
V. The head-to-head rectifier or forward rectifier behavior becomes less pronounced with
decreasing length of the writing bias pulse. The MIM structure cannot be set to LRS with
-2 -1 0 1 2
0
40
80
120
-2 -1 0 1 2
0
5
10
+8 V
+7 V
+6 V
+4 V
Curr
en
t (n
A)
Voltage (V)
100 ms
-4 V
-6 V
-7 V
-8 V
Curr
ent (n
A)
Voltage (V)
100 ms
-2 -1 0 1 2
0
40
80
120
-2 -1 0 1 2
0
10
20
100 ms
50 ms
10 ms
1 ms
Curr
en
t (n
A)
Voltage (V)
+8 V
500 ns
1 s
10 s
100 ms
Curr
ent
(nA
)
Voltage (V)
-8 V
-2 -1 0 1 2
0
20
40
60
HRS
+20 V, 500 ns
-12 V, 500 ns
Cu
rre
nt
(nA
)
Voltage (V)
LRS
(b) (a)
Figure 4.6: (a) I−V curves (ramped from −2 V to +2 V) measured after applying different
magnitudes of writing bias with the pulse length of 100 ms; (b) I−V curves
(ramped from −2 V to +2 V) measured after applying different lengths of
writing bias with the magnitude of 8 V; (c) I-V curves measured from -2 V to
+2 V after setting the MIM structure to LRS (black) by a writing bias of +20
V and 500 ns, and after resetting the MIM structure to HRS (red) by a writing
bias of -12 V and 500 ns.
(c)
4.3 Resistive switching mechanism
50
the writing bias pulse length smaller than 10 ms, while the MIM structure cannot be reset
to HRS when the pulse length is smaller than 1 µs. These results suggest that it is easier
to reset to HRS from LRS than to set to LRS from HRS, i.e. the HRS can be reset by the
writing bias pulse with smaller magnitude and smaller length. This is because of the
concentration gradient of 𝑉𝑂∙ in LRS and the asymmetric potential wells induced by Ti4+
as shown in Figure 4.5 (a larger potential barrier has to be overcome for the migration of
mobile 𝑉𝑂∙ from top interface to bottom interface than that for the migration from bottom
interface to top interface). With large magnitude of the writing bias, a resistive switching
device with fast speed can be realized, e.g. the MIM structure can be fully set/reset to
LRS/HRS within 500 ns by a writing pulse magnitude of +20 V/-12 V as shown in Figure
4.6 (c), which further confirms that the resistive switching is not attributed to the
ferroelectric switching. Note that the writing pulse length can be greatly reduced by a
minor increase of the writing bias amplitude because the drift velocity of 𝑉𝑂∙ nonlinearly
increases with increasing electric field,[165] which can be used to overcome the voltage-
time dilemma.[152] By tuning the magnitude and length of the writing bias pulse, the
resistive switching device can be continuously configured between the two fully switched
LRS/HRS states for the multilevel nonvolatile memory applications.
4.4 Tunable Schottky barrier heights
In the following we will discuss the variation of the Schottky barrier heights at top
interface and at bottom interface in LRS and HRS. We expect that the Schottky barrier
height at top interface in LRS (φt') is larger than the Schottky barrier height at top
interface in HRS (φt) because of the different 𝑉𝑂∙ distribution in LRS and HRS (Figure
4.5 (a)). Furthermore, due to the rather homogenous distribution of 𝑉𝑂∙ in HRS, we expect
that the Schottky barrier height at top interface in HRS (φt) is comparable to the Schottky
barrier height at bottom interface in HRS (φb). The temperature-dependent I-V
characteristics (from -2 V to +2 V) were measured after the Au-BFO-Pt/Ti/Sapphire
MIM structure was fully switched to HRS and LRS at room temperature as shown in
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
51
Figure 4.7 (a) and (b), respectively. The current increases with the increasing temperature
from 253 K to 348 K.
-2 -1 0 1 21E-13
1E-11
1E-9
1E-7
1E-5
HRS
348 K
323 K
298 K
273 K
253 K
|Cu
rre
nt| (
A)
Voltage (V)
on Pt/Ti/Sapphire
-2 -1 0 1 21E-13
1E-11
1E-9
1E-7
1E-5
348 K
323 K
298 K
273 K
253 K
|Curr
ent| (
A)
Voltage (V)
on Pt/Ti/SapphireLRS
2.8 3.2 3.6 4.0
-32
-30
-28
-26
-24
0.7 0.8 0.9 1.0 1.1 1.2
0.19
0.20
-1.4 V
-1.2 V
-1.0 V
-0.8 V
-0.6 V
Ln
(J/T
3/2)
1000/T
t (
eV
)
|V|1/2
t0=0.16 eV
2.8 3.2 3.6 4.0
-32
-30
-28
-26
-24
0.7 0.8 0.9 1.0 1.1 1.2
0.18
0.19
0.20
0.21
+0.6 V
+0.8 V
+1.0 V
+1.2 V
+1.4 V
Ln
(J/T
3/2)
1000/T
b (
eV
)
|V|1/2
b0
=0.13 eV
240 260 280 300 320 340 360
0.8
0.9
1.0
1.1
' t (
eV
)
Temperature (K)
3
4
5
Ide
ality
Facto
r
(b)
(a)
Figure 4.7: Temperature dependent I-V characteristics for HRS (a) and LRS (b) in Au-
BFO-Pt/Ti/Sapphire MIM structure. Schottky−Simmons representation of
the (c) negative bias range and (d) positive bias range for HRS. The insets
indicate the zero bias Schottky barrier heights formed on top (φt0) and bottom
(φb0) interface in Au-BFO-Pt/Ti/Sapphire MIM structure. (e) Temperature-
dependent zero bias Schottky barrier height and ideality factor for LRS in Au-
BFO-Pt/Ti/Sapphire.
(d) (c)
(e)
4.4 Tunable Schottky barrier heights
52
4.4.1 Schottky barrier heights in HRS
In HRS, the current is small in both the positive and negative bias range due to the
Schottky-like barriers formed at both top and bottom interfaces. As discussed in Chapter
2.3.2, the reverse current of two anti-serially connected Schottky barriers can be
governed by Poole-Frenkel emission, Schottky emission, or modified Schottky emission.
As listed in Table 4.1, the corresponding emission coefficients are calculated according
Eq. 2.8 and fitted from the plot of ln(I/E) vs. E1/2, ln(I/T2) vs. E1/2, and ln(I/ET3/2) vs. E1/2
for Poole-Frenkel emission, Schottky emission, and modified Schottky emission,
respectively. By comparing the calculated and fitted emission coefficients, it suggests
that the modified Schottky emission dominates the electric conduction under reverse bias
condition as the fitted emission coefficients for modified Schottky emission are more
close to the calculated ones in comparison to that for Poole-Frenkel emission and
Schottky emission. The I-V characteristics can be described by the modified Richardson-
Schottky equation Eq. (2.7).
The apparent potential barrier for the respective constant voltage can be estimated from
the slope of the representation ln (J/T3/2)~1/T which should give a straight line. Figure
4.7 (c) and (d) show the ln(J/T3/2)~1000/T plot together with the linear fitting in negative
and positive bias range, respectively. Further on, representing the obtained apparent
potential barrier value (φt in inset of Figure 4.7 (c) and φb in inset of Figure 4.7 (d)) as a
function of V1/2, the potential barrier at zero bias (φt0 and φt0) can be extracted from the
intercept at φt and φb axes. In HRS, the current is blocked by the Schottky-like barrier at
top interface (φt) in negative bias range, while the current is blocked by the Schottky-like
Table 4.1: Calculated and fitted coefficients (S) in both positive and negative bias for Poole-
Frenkel emission (PFE), Schottky emission (SE), and modified Schottky
emission (MSE) at different temperatures for HRS in Au-BFO-Pt/Ti/Sapphire.
SPFE SSE SMSE
T (K) Calculated Fitted (V>0 V) Fitted (V<0 V) Calculated Fitted (V>0 V) Fitted (V< 0 V) Calculated Fitted (V>0 V) Fitted (V<0 V)
253 0.00070 0.00154 0.00214 0.00139 0.00335 0.00424 0.00139 0.00154 0.00214
273 0.00064 0.00149 0.00198 0.00129 0.00293 0.00407 0.00129 0.00149 0.00198
298 0.00059 0.00200 0.00214 0.00118 0.00412 0.00423 0.00118 0.00200 0.00214
323 0.00054 0.00167 0.00195 0.00109 0.00325 0.00404 0.00109 0.00167 0.00195
348 0.00051 0.00197 0.00174 0.00101 0.00331 0.00383 0.00101 0.00197 0.00174
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
53
barrier at bottom interface (φb) in positive bias range. Therefore, the zero bias Schottky
barrier heights in HRS at top and bottom interfaces (φt0 and φb0) can be extracted from
the plot in negative and positive bias range, respectively, which are deduced to be 0.16
eV (φt0) and 0.13 eV (φb0), respectively.
4.4.2 Schottky barrier heights in LRS
In LRS, the current is mainly dominated by the Schottky-like barrier at top interface. As
introduced in Chapter 2.3.1, the electric transport of a single Schottky barrier can be
described by the Shockley equation Eq. (2.1). As shown in Figure 4.7 (e), the zero bias
Schottky barrier height and ideality factor can be fitted from the temperature dependent
I-V characteristics in LRS (Figure 4.7 (b)) by using Eq. (2.1). With the increasing
temperature from 253 K to 348 K, the ideality factor decreases from 4.42 to 3.22 and the
zero bias Schottky barrier height in LRS at top interface (φt0') increases from 0.81 eV to
1.09 eV. This suggests that the zero bias Schottky barrier height at top interface is greatly
increased when the MIM structure is set to LRS with 𝑉𝑂∙ drifting towards the bottom
interface. The relatively large ideality factor indicates the deviation of I-V characteristics
from thermionic emission theory. This may be due to the large series resistance in the
order of megaohm and the lateral inhomogeneity of the Schottky barrier height which
becomes more pronounced as the temperature decreases. Because electrons possess a
small kinetic energy at low temperature, they prefer to pass through the lowest barrier.
4.5 Local resistive switching
The lateral inhomogeneity of the Schottky barrier height is evidenced by conductive
AFM measurements on Au-BFO-Pt/Ti/Sapphire MIM structure as shown in Figure 4.8.
The AFM topography of the as-grown BFO thin film with a scanning size of 2×2 µm2 is
shown in Figure 4.8 (a), which indicates a surface roughness of 12.5 nm. Figure 4.8 (b)
shows the local I-V characteristics which were measured by putting the top conductive
tip on the surface of BFO thin film. An obvious resistive switching is observed in the
negative bias range. Note that the bias polarity is opposite to the I-V measurements
shown in Figure 4.1 (a), because the voltage bias is applied on the Pt bottom electrode as
4.5 Local resistive switching
54
indicated in the inset of Figure 4.8 (b). The size of the top conductive tip is 20 nm. The
local area with the size of 2×2 µm2 can be switched to LRS or HRS by scanning the
conductive tip with a voltage bias of -10 V or +10 V on the Pt bottom electrode. Figure
4.8 (c) and (d) show the current images in LRS and HRS, respectively. The reading bias
was -4 V, as the difference between LRS and HRS is not visible in linear scale until -4 V
in the local I-V characteristic as shown in Figure 4.8 (b). In HRS only some small leakage
current is observed, while in LRS some conductive areas appear in some grains. The local
resistive switching suggests the possibility to scale down the resistive switching cell to
-10 -5 0 5 10-0.06
-0.03
0.00
0.03
0.06
LRS
1st: -10 V to +10 V
2nd
: +10 V to -10 V
3rd: -10 V to +10 V
4th: +10 V to -10 V
Cu
rre
nt
(nA
)
Sample Bias (V)
HRS
Figure 4.8: (a) AFM topography image of as-prepared BFO thin film with a scanned size
of 2×2 μm2. (b) Local I-V characteristics measured with the conductive tip on
the surface of BFO thin film. The current images measured from (c) LRS and
(d) HRS with a reading bias of -4 V applied on the Pt bottom electrode. The
inset in (b) shows the schematic of the conductive AFM measurements on
BFO-Pt/Ti/Sapphire. The voltage is applied on the Pt bottom electrode, and
the top conductive tip is grounded, which is opposite to the I-V measurements
shown in Figure 4.1.
(a)
(c) (d)
(b) 140 nm
20 nm
LRS -5 pA
-8 pA
HRS -5 pA
-8 pA
4 Resistive switching in BiFeO3 thin films with a single tunable barrier
55
the grain size. The grain size is a function of film thickness and thermal budget of the
deposition and post processing. Lateral and vertical dimensions have to be scaled and
thermal treatments have to be tuned accordingly. Recently it was shown that excellent
switching data can be achieved for scaled electrodes and significantly reduced film
thickness.[166] Even though Figure 4.8 (c) and (d) show the inhomogeneous distribution
of the current, the resistive switching does not come from the formation and rupture of
filaments as discussed in Chapter 4.3, which indicates the lateral inhomogeneity of the
Schottky barrier height and the conductive shunts formed by the defects existing in the
BFO bulk.[41, 167] Possibly, a larger writing voltage is required to switch the highly
resistive locations with high Schottky barrier height or without the conductive shunts.
4.6 Conclusions
In this chapter, polycrystalline BFO thin films have been prepared by the PLD process
on Pt/Ti/Sapphire, Pt/Ti/SiO2/Si, and Pt/Sapphire substrates. The I-V characteristics
suggest that the electroforming-free bipolar resistive switching exists only in Au-BFO-
Pt/Ti/Sapphire and Au-BFO-Pt/Ti/SiO2/Si MIM structures, but not in Au-BFO-
Pt/Sapphire MIM structure. The TEM and EDX mapping results reveal that the Ti
diffusion occurs during the BFO deposition process, which plays a crucial role in the
electroforming-free bipolar resistive switching in Au-BFO- Pt/Ti/Sapphire and Au-BFO-
Pt/Ti/SiO2/Si MIM structures. The resistive switching behavior can be explained by a
model of tunable Schottky barrier height at BFO-Pt bottom interface, in which the 𝑉𝑂∙
acts as mobile donor and Ti4+ acts as fixed donor. The distribution of mobile 𝑉𝑂∙ donors
can be changed by the writing bias, i.e. the mobile 𝑉𝑂∙ donors can be trapped and released
by the fixed Ti4+ donors, which changes the Schottky barrier height at BFO-Pt bottom
interface and consequently changes the resistance state of the MIM structures. The top
and bottom Schottky barrier heights in LRS and HRS were extrapolated from the
temperature dependent I-V characteristics. Due to the redistribution of mobile 𝑉𝑂∙ donors
after the writing bias, a degradation is observed in the retention tests. The endurance can
be improved by introducing a rough BFO-Pt bottom interface thanks to the local electric
field enhancement around the protrusions. The resistive switching can be continuously
4.6 Conclusions
56
configured by tuning the amplitude and length of the writing bias pulse, which makes it
possible to realize the multilevel resistive switching and to increase the switching speed.
The local resistive switching revealed by the conductive AFM measurements suggests
the possibility to scale down the resistive switching cell to the grain size.
57
Chapter 5 Engineering resistive switching by Ti
implantation of bottom electrodes
In Chapter 4, BFO thin films have been fabricated on Pt/Ti/Sapphire or Pt/Ti/SiO2/Si
substrates by PLD process and shown excellent bipolar resistive switching performances
such as electroforming free, multi-level states, long retention time, and stable endurance.
A model based on the tunable Schottky barrier height was proposed to explain the bipolar
resistive switching in BFO thin films, in which the charged oxygen vacancies 𝑉𝑂∙ and
diffused Ti act as mobile and fixed donors, respectively. The mobile 𝑉𝑂∙ donors are
redistributed by a writing bias which tunes the Schottky barrier height at the bottom
interface and consequently changes the resistance state of the MIM structures, and the
fixed Ti donors can trap the mobile 𝑉𝑂∙ donors after the writing process to stabilize the
resistive switching. It has been evidenced that the Ti diffusion from the bottom electrodes
during BFO thin film deposition is crucial for the electroforming free bipolar resistive
switching, and it was reported that the diffused metallic atoms from the bottom electrodes
or even from the adhesion layer under the bottom electrodes seed the nanoscale switching
centers in the resistive switching devices.[168] However, technically, the metallic
diffusion from the bottom electrodes or the adhesion layer is often poorly controlled and
restrains the options of metallic materials used for the bottom electrodes. Additionally,
the metallic diffusion often occurs over the whole wafer chip which is in contradiction
with the CMOS compatible technologies.
In this Chapter, we show that the Ti diffusion can be engineered before the BFO thin film
deposition by Ti implantation of the Pt bottom electrode on sapphire substrates. The
effect of the Ti implantation fluences on the resistive switching characteristics of the
5.1 Device fabrication and material characterization
58
fabricated BFO-based MIM structures is investigated, which offers a deeper
understanding on the role of the fixed Ti donors in the resistive switching of BFO-based
MIM structures.
5.1 Device fabrication and material characterization
5.1.1 Fabrication of Au-BFO-Pt MIM structures with different Ti fluences
As shown in Figure 5.1, the Ti implantation of Pt(100 nm)/Sapphire substrates was first
carried out at room temperature with an ion energy of 40 keV and a series of Ti fluences.
The Ti fluences are 5×1015 cm-2, 1×1016 cm-2, and 5×1016 cm-2. Subsequently, BFO thin
films with a thickness of 460 nm were deposited on the Ti-implanted Pt/Sapphire
substrates by the same PLD process as introduced in Chapter 3.1. The nominal laser
energy density, laser repetition rate, oxygen ambient pressure, and growth temperature
were 2.6 J/cm2, 10 Hz, 0.013 mbar, and 650 °C, respectively. After the BFO deposition,
the BFO thin films were in-situ annealed at 390 °C with a nominal oxygen ambient
pressure of 200 mbar for 60 minutes. Following the PLD process, circular Au top contacts
with an area of 0.045 mm2 and a thickness of 110 nm were prepared by DC magnetron
sputtering at room temperature using a metal shadow mask. Thus, Au-BFO-Pt MIM
structures with different Ti fluences were fabricated.
Figure 5.1: Schematic of the fabrication process and the measurement setups for the Au-
BFO-Pt MIM structure with different Ti fluences.
Pt/Sapphire Ti implantation BFO deposition
Au top electrode fabrication
V
Electrical measurement
CsAFM measurement
AuBFOTiPtSapphire
5 Engineering resistive switching by Ti implantation of bottom electrodes
59
5.1.2 Ti distribution in Pt/Sapphire and surface morphology of Pt/Sapphire
The Ti distribution in the Pt/Sapphire after the Ti implantation was estimated by the
Stopping and Range of Ions in Matter (SRIM) 2013 code.[169, 170] The predicted
0 10 20 3010
-1
101
103
105
Ti diff
usion
SapphirePtBFOAu
Au
Pt
Al
Ti
Fe
Inte
nsity (
a.u
.)
Sputtering Time (min)
Bi
0 50 100
0
10
20
5x1016
cm-2
1x1016
cm-2
5x1015
cm-2
Ato
ms (
x10
21 c
m-3)
Depth (nm)
Sapp
hir
e
Surf
ace
Pt(b) (a)
(d) (c)
Figure 5.2: (a) Calculated depth distribution of implanted Ti ions in Pt/Sapphire
substrates using SRIM 2013. (b) Tof-SIMS intensity-time profiles of the
metallic elements in the MIM structure with Ti fluence of 5 × 1016 cm−2.
Three-dimensional AFM topography images of (c) the pristine Pt/Sapphire
and the Ti-implanted Pt/Sapphire with Ti fluence of (d) 5×1015 cm−2, (e)
1×1016 cm−2, and (f) 5×1016 cm−2. The scanning size is 3×3 μm2. The mean
arithmetic roughness (Ra) is 3.98 nm, 2.24 nm, 1.15 nm, and 4.99 nm,
respectively. The AFM color scale (right side) indicates the height
information.
(f) (e)
5.1 Device fabrication and material characterization
60
concentrations of implanted Ti ions as a function of depth in Pt/Sapphire with different
Ti fluences are shown in Figure 5.2 (a). It can be seen that Ti ions distribute within 50
nm below the surface of Pt layer and a concentration peak forms at the depth of ~10 nm.
Note that SRIM as a static Monte Carlo program can only estimate the Ti distribution
under the assumption that the initial stoichiometry of Pt/Sapphire is preserved. A
sputtering yield of 9.36 for Pt was calculated by SRIM 2013, which suggests that around
15% of Pt atoms could be sputtered away at the Ti concentration peak with Ti fluence of
5×1016 cm-2. Experimentally, the Pt layer was completely removed when the Ti fluence
was further increased, e.g. 1×1017 cm-2. The Ti implantation effect on the surface
morphology of Pt/Sapphire was investigated by AFM with a scanning size of 3×3 µm2
as shown in Figure 5.2 (c)-(f). Pt grains with a typical size of 80 nm randomly distribute
over the pristine Pt/Sapphire, and the mean arithmetic roughness (Ra) is 3.98 nm. After
Ti implantation at low fluence of 5×1015 cm-2, the roughness is reduced to 2.24 nm. By
further increasing the fluence to 1×1016 cm-2, the roughness is reduced to 1.15 nm, which
may be due to the strain relaxation between the grains caused by the energy deposited by
the implanted Ti ions. However, by further increasing the Ti fluence to 5×1016 cm-2, the
typical Pt grain size dramatically increases to 170 nm, which may be due to the
appearance of the disordering induced agglomeration of grains. Consequently, the
roughness is increased to 4.99 nm. A comparable dependence of surface roughness on
ion fluence has also been observed for ZnO thin films irradiated by Au ions.[171]
5.1.3 Ti distribution in BFO thin films and surface morphology of BFO thin films
It is expected that the Ti migration into BFO layer is more efficient along the BFO grain
boundaries and occurs during the PLD process at 650 °C.[172] Figure 5.2 (b) shows the
Tof-SIMS intensity-time profiles of the BFO thin film on Ti-implanted Pt/Sapphire with
Ti fluence of 5×1016 cm-2, depicting Au, Bi, Fe, Ti, Pt, and Al ion intensities as a function
of sputtering time. It is clear that the Ti intensity profile exhibits a broader shoulder
compared to that of other metallic elements, which indicates that Ti diffused into the BFO
thin films during the PLD process and that a Ti concentration gradient was created along
the BFO growth direction. The Ti diffusion into BFO was also observed in the BFO thin
films on Pt/Ti/Sapphire or Pt/Ti/SiO2/Si substrates in our previous works,[172, 173]
5 Engineering resistive switching by Ti implantation of bottom electrodes
61
which plays a crucial role for the resistive switching in BFO thin films as discussed in
Chapter 4. In these MIM structures, Pt layer serves not only as a bottom electrode but
also as a diffusion suppressing layer to prevent a strong Ti diffusion into BFO layer
during the BFO deposition at 650 °C. Therefore, an optimized concentration of fixed Ti
donors is realized and a tunable Schottky can be formed at the BFO-Pt/Ti interfaces. It is
expected that less Ti diffuses into the BFO layer in MIM structures with Pt bottom
electrodes which have been implanted with a smaller Ti fluence. The surface morphology
of the BFO thin films on Ti-implanted Pt/Sapphire was characterized by AFM
measurements with a scanning size of 3×3 µm2. The mean arithmetic surface roughness
of BFO thin films is 12.5 nm, 9.54 nm, and 13.1 nm for the Ti fluence of 5×1015 cm-2,
1×1016 cm-2, and 5×1016 cm-2, respectively.
5.2 Resistive switching characteristics
5.2.1 I-V characteristics
The I-V measurements were carried out with a Keithley 2400 source meter. The
schematic sketch of the electrical measurement configuration is indicated in Figure 5.1,
in which the bias voltage was applied on Au top electrode and the Ti-implanted Pt bottom
electrode was grounded. As shown in Figure 5.3, the shape of the I-V characteristics
obtained from the BFO on Ti-implanted Pt/Sapphire is quite similar to that presented in
Chapter 4. The I-V characteristics were measured by sweeping the voltage in sequence
of 0 V +8 V -8 V 0 V (black curve) and 0 V -8 V +8 V 0 V (red curve)
on two pristine cells of the MIM structures, respectively. In both cases, a distinct I-V
hysteresis exists in the positive bias range and no significant difference in the I-V
characteristics with different voltage sweeping sequences is observed, which suggests
that the electroforming process is not required for the resistive switching. Initially, the
pristine MIM structures show HRS, and LRS is set by a positive bias while the HRS is
reset by a negative bias. This indicates a bipolar resistive switching without an
electroforming process for the MIM structures with different Ti fluences. Note that BFO
thin films deposited on non-implanted Pt/Sapphire substrates do not show distinct
5.2 Resistive switching characteristics
62
resistive switching behavior as shown in Figure 4.2 (c).[173] Within the same applied
bias range (between -8 V and +8 V) there is no obvious current difference in the negative
bias range for the MIM structures with different Ti fluences, while the current in the
positive bias range and the on/off current ratio at +2 V increase with increasing Ti fluence
as shown in Figure 5.3 (d).
Figure 5.3: Typical I-V characteristics with different voltage sweeping sequences
measured at two pristine cells on the MIM structures with Ti fluence of (a)
5×1015 cm−2, (b) 1×1016 cm−2, and (c) 5×1016 cm−2. The insets show the I-V
characteristics with the same voltage sweeping sequences but different
maximum voltage measured at the same cell on the MIM structures. Note
that to avoid a hard breakdown of the devices, the maximum current was
limited to be 100 μA. The sets of the maximum voltages are [8.0 V, 9.0 V,
10.0 V], [8.0 V, 8.5 V, 9.0 V] and [6.0 V, 7.0 V, 8.0 V] for the MIM
structures with Ti fluence of 5×1015 cm−2, 1×1016 cm−2, and 5×1016 cm−2,
respectively. The numbers (1)–(4) and the arrows indicate the voltage
sweeping sequences and the voltage sweeping directions, respectively. (d)
Current at +8 V and -8 V and on/off current ratio at +2 V from the I-V
characteristics shown in (a), (b), and (c).
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
(4)
(3)
(2)
5x1015
cm-2
|Curr
ent| (
A)
Voltage (V)
0 V +8 V -8 V 0 V
0 V -8 V +8 V 0 V
LRS
HRS
(1)
(3)
(1)
(4)(2)
(3)(1)
(2)
(4)
10.0 V
9.0 V
8.0 V
|Cu
rren
t| (
A)
Voltage (V)
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
1x1016
cm-2 0 V +8 V -8 V 0 V
0 V -8 V +8 V 0 V
|Cu
rre
nt| (
A)
Voltage (V)
HRS
LRS(1)
(2)
(3)
(4)
(3)
(1)
(4)(2)
(1)(3)
(4)
(2)
9.0 V
8.5 V
8.0 V
Voltage (V)
|Cu
rren
t| (
A)
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
(4)(2)
(3)
LRS
|Cu
rre
nt| (
A)
Voltage (V)
0 V +8 V -8 V 0 V
0 V -8 V +8 V 0 V
HRS
5x1016
cm-2
(1)
(2)
(3)
(4)
(1)(3)(1)
(4)(2)
8.0 V
7.0 V
6.0 V
|Cu
rren
t| (
A)
Voltage (V)
1E-7
1E-6
1E-5
1E-4
1E-3
On/Off ratio @ +2 V
Current @ -8 V
5010
|Cu
rre
nt| (
A)
Ti fluence (x1015
cm-2)
5
Current @ +8 V
101
102
103
On
/Off
ra
tio
@ +
2 V
(a) (b)
(c) (d)
5 Engineering resistive switching by Ti implantation of bottom electrodes
63
The work function of Au and Pt amounts to 5.1 eV and 5.3 eV, respectively. The band
gap of BFO is taken as 2.8 eV and the electron affinity is 3.3 eV,[151] and then the work
function of n-type BFO should be less than 4.7 eV, which suggests an upward band
bending in BFO at top Au-BFO and bottom BFO-Pt interfaces. Therefore, a Schottky
barrier can be formed at both top and bottom interfaces. The observed resistive switching
characteristics in BFO based MIM structures with different Ti fluences can also be
explained by a model of tunable Schottky barrier height at bottom interface which can be
tuned by the mobile 𝑉𝑂∙ acting as the mobile donors as shown in Figure 4.5.[173] With
lower Ti fluence, a larger Schottky barrier height is expected to form at the bottom
interface which will be discussed later. Therefore, a larger electric field is required to
move the 𝑉𝑂∙ to the bottom interface to reduce the Schottky barrier height to fully set the
structures to LRS. The insets in Figure 5.3 (a)-(c) show the I-V characteristics with
different maximum voltages. The paths for the I-V curves in negative bias range
(branches (3) and (4)) and the HRS branch of the I-V curve in positive bias range (branch
(1)) are nearly the same which are independent of the maximum voltage. While the LRS
branch of the I-V curve in positive bias range (branch (2)) are well separated from each
other with different maximum voltage, indicating different LRS can be achieved
depending on the applied maximum voltages. This multilevel LRS behavior offers an
opportunity for designing multi-bit memories/logics.[174]
5.2.2 Retention and endurance tests
As shown in Figure 5.4 (a), the retention tests were carried out by first setting/resetting
the MIM structures to LRS/HRS at room temperature, and then detecting the current with
a small reading bias of +2 V every 2 min at room temperature (for the MIM structure
with Ti fluence of 5×1016 cm-2, the current detection was performed at 358 K as well). In
order to fully set/reset the MIM structures to LRS/HRS, the set/reset bias of +10 V/-10
V, +9 V/-9 V and +8 V/-8 V with pulse length of 100 ms were used for the MIM
structures with Ti fluence of 5×1015 cm-2, 1×1016 cm-2, and 5×1016 cm-2, respectively. At
room temperature, the HRS for all MIM structures are relatively stable, while degradation
is observed during the LRS tests. The LRS of the MIM structures with low Ti fluences
(both 5×1015 cm-2 and 1×1016 cm-2) decreases continuously during the retention tests, and
5.2 Resistive switching characteristics
64
the current ratio ILRS/IHRS of the MIM decreases below 10 within 24 hours, while the LRS
of the MIM structure with high Ti fluence (5×1016 cm-2) becomes stable after around 15
hours. The extrapolated current ratio ILRS/IHRS can be well-kept at around 50 for more
than 10 years as indicated by the dashed lines in Figure 5.4 (a). Even at an elevated
temperature of 358 K, the LRS of the MIM structure with Ti fluence of 5×1016 cm-2 can
be stabilized within 24 hours and a current ratio ILRS/IHRS larger than 30 can be obtained
for more than 10 years. The HRS at elevated temperature initially exhibits a small decay.
The similar effect was also observed in Au-BFO-Pt/Ti/Sapphire MIM structures, which
101
103
105
107
109
1E-10
1E-8
1E-6
5x1016
cm-2 @ 358 K
5x1016
cm-2 @ RT
1x1016
cm-2 @ RT
5x1015
cm-2 @ RT
|Curr
ent| (
A)
Time (s)
10 y
ears
LRS
HRS
100
101
102
103
104
105
0.01
0.1
1
5x1016
cm-2 @ 358 K
5x1016
cm-2 @ RT
1x1016
cm-2 @ RT
5x1015
cm-2 @ RT
I t/I0
Time (s)
1 10 100 1000 100001E-10
1E-8
1E-6
HRS
5x1016
cm-2
1x1016
cm-2
5x1015
cm-2
Cu
rre
nt
(A)
Cycles
@ RT
LRS
6.0 6.410
0
102
104
Co
un
t
Log (R)
5x1016
cm-2
1x1016
cm-2
5x1015
cm-2
LRS
8.2 8.6 9.0
HRS
(b) (a)
(d) (c)
Figure 5.4: (a) Retention test results of the MIM structures with different Ti fluences.
The extrapolated 10-years HRS/LRS retention time can be expressed by the
dashed lines. (b) Normalized current of LRS vs. retention time. The current
values taken at different time (It) are normalized by the initially measured
current value (I0). (c) Endurance test results of the MIM structures with
different Ti fluences. (d) Statistics histograms of LRS/HRS in the endurance
test results.
5 Engineering resistive switching by Ti implantation of bottom electrodes
65
was possibly due to the redistribution of 𝑉𝑂∙ in HRS at elevated temperature as discussed
in Chapter 4.[173]
Figure 5.4 (b) shows the normalized current in LRS, which suggests that the degradation
in LRS becomes more pronounced with decreasing Ti fluence. In LRS the 𝑉𝑂∙ migrate to
the bottom interface and then are trapped by the diffused Ti from the substrates during
the BFO deposition, which consequently increases the doping concentration at the bottom
interface and lowers the bottom Schottky barrier height as discussed in Chapter 4.3. The
degradation in LRS is possibly due to the back diffusion of 𝑉𝑂∙ after the application of a
positive writing voltage pulse which partially decreases the doping concentration at the
bottom interface and partially starts to rebuild the bottom Schottky barrier. With lower
Ti fluence, during the PLD process less Ti can diffuse from the hot Pt bottom electrode
into the BFO layer. Therefore, not enough 𝑉𝑂∙ can be effectively trapped by Ti and the
LRS is badly maintained. The degradation of LRS in MIM structure with Ti fluence of
5×1016 cm-2 is stronger at an elevated temperature of 358 K because of the increasing
diffusivity of 𝑉𝑂∙ with increasing temperature. This suggests that a certain minimum
amount of Ti in the BFO MIM structures is required to trap the mobile 𝑉𝑂∙ in the bottom
interface in order to stabilize the resistive switching into LRS.
As shown in Figure 5.4 (c), the endurance tests were carried by repeating the process of
set/read/reset/read for more than 3×104 times at room temperature. Figure 5.4 (d) shows
the statistics histograms of the LRS/HRS in the endurance test results. In endurance tests,
all MIM structures with different Ti fluences possess a relatively stable LRS and a narrow
distribution of the resistance values in LRS. The relative fluctuation (standard deviation
divided by mean value)[150] of LRS is 0.20%, 0.91%, and 0.82% for the MIM structures
with Ti fluence of 5×1015 cm-2, 1×1016 cm-2, and 5×1016 cm-2, respectively. However, the
distribution of the resistance values in HRS is much broader than that in LRS. The
relative fluctuation increases with the Ti fluences, i.e., 1.11%, 3.95%, and 12.34% for the
MIM structures with a Ti fluence of 5×1015 cm-2, 1×1016 cm-2, and 5×1016 cm-2,
respectively. The endurance can be improved by structuring the bottom electrodes or by
local Ti-implantation into the bottom electrodes.[150, 151, 173]
5.3 Dependence of Schottky barrier height on the Ti fluence
66
5.3 Dependence of Schottky barrier height on the Ti fluence
5.3.1 Schottky barrier heights in HRS
The temperature-dependent I-V characteristics (from -2 V to +2 V) were measured by
Keithley 2636A source meter (with a theoretical current resolution of 0.1 fA) after the
MIM structures were fully set/reset to LRS/HRS. The current increases with the
temperature increasing from 253 K to 353 K. In HRS, the current is small in both positive
and negative bias range showing head-to-head diode behavior as the Schottky-like
Figure 5.5: (a) Bias dependent Schottky barrier heights in HRS. The zero-bias Schottky
barrier height can be extracted by a linear fitting. (b) Temperature dependent
zero-bias Schottky barrier heights and ideality factors in LRS. (c) Change of
the top and bottom Schottky barrier heights in LRS and HRS for the MIM
structures with different Ti fluences.
0.9 1.0 1.1 1.2 1.30.40
0.45
0.35
0.40
0.45
0.45
0.50
0.55
0.60
'b-HRS
=0.57 eV
|V|1/2
H
RS (
eV
)
't-HRS
=0.47 eV
5x1015
cm-2
negative bias
positive bias
1x1016
cm-2
''b-HRS
=0.26 eV
''t-HRS
=0.43 eV negative bias
positive bias
negative bias5x1016
cm-2
'''t-HRS
=0.30 eV
'''b-HRS
=0.46 eV
positive bias
260 280 300 320 340 360
0.8
0.9
1.0
Temperature (K)
5x1015
cm-2 8
12
16
0.8
0.9
1.0
1x1016
cm-2
t-L
RS (
eV
)
5
10
15
20
Ideality
Facto
r
0.8
0.9
1.0
5x1016
cm-2 5
10
15
5.0x1015
1.0x1016
1.5x1016
0.2
0.4
0.6
0.8
1.0
b-HRS
t-HRS
353 K
Ba
rrie
r H
eig
ht
(eV
)
Ti fluence (cm-2)
HRS t
HRS b
H
L
LRS
HRSb
HRSt
HRSb
HRSt
253 K
t-LRS
5.0x1016
(a) (b)
(c)
5 Engineering resistive switching by Ti implantation of bottom electrodes
67
barriers form at both top and bottom interfaces. As introduced in Chapter 2.3.2, the
reversed current of two anti-serially connected Schottky barriers can be governed by
Poole-Frenkel emission, Schottky emission or modified Schottky emission mechanisms.
Similar to that in Chapter 4.4, the corresponding calculated and fitted emission
coefficients for Poole-Frenkel emission, Schottky emission, and modified Schottky
emission are listed in Table 5.1, which suggests that electric conduction under reverse
bias condition is consistent with the modified Schottky emission as the fitted emission
coefficients for modified Schottky emission are more close to the calculated ones in
comparison to that for Poole-Frenkel emission and Schottky emission. The I-V
characteristics can be described by the modified Richardson-Schottky equation Eq. (2.7).
The apparent potential barrier for the respective constant voltage (electric field) can be
estimated from the slope of the representation of ln (J/T3/2)~1/T which gives a straight
line. The temperature dependent I-V characteristics of the MIM structures with different
Ti fluences were replotted in the Schottky-Simmons representation of ln (J/T2/3)~1/T at
voltages of ±0.8 V, ±1.0 V, ±1.2 V, ±1.4 V and ±1.6 V. A linear fitting was obtained in
both negative and positive bias range. Figure 5.5 (a) shows the apparent potential barrier
height (φHRS) calculated from the slope of the linear fitting in the plotting of ln
(J/T2/3)~1/T as a function of |V|1/2. The barrier height at top interface can be obtained
from the plotting in the negative voltages range (V<0 V) as the top Schottky barrier is
reversed and dominates the current under the negative bias, and similarly the barrier
height of reversed bottom Schottky barrier corresponds to the plotting in positive bias
range (V>0 V). As shown in Figure 5 (a), with increasing reverse bias both top and
bottom Schottky barrier heights decrease in the MIM structures with low Ti fluence
(5×1015 cm-2 and 1×1016 cm-2), while the barrier heights of the MIM structure with Ti
fluence of 5×1016 cm-2 increase. The Schottky barrier height depends on the doping
concentration and the applied reverse bias, i.e. the Schottky barrier height decreases with
increasing reversed bias in the case of low doping concentration but increases in the case
of high doping concentration.[175] With larger Ti fluence, more Ti diffuses into BFO
during the PLD process and the as-prepared BFO thin film possesses a higher doping
concentration. Therefore, different changes of the Schottky barrier heights are presented.
The potential barrier at zero bias can be extracted from the intercept of the linear fitting
5.3 Dependence of Schottky barrier height on the Ti fluence
68
in the apparent potential barrier height as a function of |V|1/2. The top Schottky barrier
height (φt-HRS) is deduced to be 0.47 eV, 0.43 eV, and 0.30 eV for the MIM structures
with Ti fluence of 5×1015 cm-2, 1×1016 cm-2, and 5×1016 cm-2, respectively, and the
corresponding bottom one (φb-HRS) is 0.57 eV, 0.46 eV and 0.26 eV, respectively.
Table 5.1: Calculated and fitted coefficients (S) in both positive and negative bias for Poole-
Frenkel emission (PFE), Schottky emission (SE), and modified Schottky emission
(MSE) at different temperatures for the MIM structures with Ti fluence of 5×1015
cm-2 (I), 1×1016 cm-2 (II), and 5×1016 cm-2 (III).
(I) SPFE SSE SMSE
T (K) Calculated Fitted (V>0 V) Fitted (V<0 V) Calculated Fitted (V>0 V) Fitted (V< 0 V) Calculated Fitted (V>0 V) Fitted (V<0 V)
253 0.00070 0.00215 0.00138 0.00139 0.00360 0.00283 0.00139 0.00215 0.00138
273 0.00064 0.00193 0.00091 0.00129 0.00338 0.00235 0.00129 0.00193 0.00091
293 0.00060 0.00134 0.00094 0.00120 0.00279 0.00238 0.00120 0.00134 0.00094
313 0.00056 0.00178 0.00095 0.00112 0.00322 0.00240 0.00112 0.00178 0.00095
333 0.00053 0.00092 0.00076 0.00106 0.00217 0.00220 0.00106 0.00092 0.00076
353 0.00050 0.00076 0.00060 0.00100 0.00191 0.00204 0.00100 0.00076 0.00060
(II) SPFE SSE SMSE
T (K) Calculated Fitted (V>0 V) Fitted (V<0 V) Calculated Fitted (V>0 V) Fitted (V< 0 V) Calculated Fitted (V>0 V) Fitted (V<0 V)
253 0.00070 0.00171 0.00333 0.00139 0.00316 0.00478 0.00139 0.00171 0.00333
273 0.00064 0.00236 0.00262 0.00129 0.00383 0.00407 0.00129 0.00239 0.00262
293 0.00060 0.00191 0.00155 0.00120 0.00336 0.00300 0.00120 0.00191 0.00155
313 0.00056 0.00207 0.00199 0.00112 0.00352 0.00343 0.00112 0.00207 0.00199
333 0.00053 0.00126 0.00110 0.00106 0.00270 0.00255 0.00106 0.00126 0.00110
353 0.00050 0.00085 0.00087 0.00100 0.00200 0.00212 0.00100 0.00085 0.00087
(III) SPFE SSE SMSE
T (K) Calculated Fitted (V>0 V) Fitted (V<0 V) Calculated Fitted (V>0 V) Fitted (V< 0 V) Calculated Fitted (V>0 V) Fitted (V<0 V)
253 0.00070 0.00126 0.00148 0.00139 0.00121 0.00153 0.00139 0.00126 0.00148
273 0.00064 0.00090 0.00091 0.00129 0.00234 0.00236 0.00129 0.00090 0.00091
293 0.00060 0.00094 0.00105 0.00120 0.00219 0.00157 0.00120 0.00094 0.00105
313 0.00056 0.00145 0.00162 0.00112 0.00289 0.00307 0.00112 0.00145 0.00162
333 0.00053 0.00168 0.00131 0.00106 0.00312 0.00276 0.00106 0.00168 0.00131
353 0.00050 0.00151 0.00184 0.00100 0.00296 0.00329 0.00100 0.00151 0.00184
5.3.2 Schottky barrier heights in LRS
In LRS, the I-V characteristics exhibit forwarded diode behavior due to the Schottky
contact at top interface and Ohmic contact at bottom interface, and the current is mainly
dominated by the Schottky barrier at top interface as discussed in Chapter 4. As shown
in Figure 5.5 (b), the temperature dependent zero bias Schottky barrier height and ideality
factor were fitted from the temperature dependent I-V curves by using the Shockley
5 Engineering resistive switching by Ti implantation of bottom electrodes
69
equation Eq. (2.1) introduced in Chapter 2.3.1. The obtained Schottky barrier height (φt-
LRS) at the top interface decreases with the increasing temperature, while the ideality
factor increases. The relatively large ideality factor may be due to the large series
resistance in the order of several mega-ohm. By comparing the top and bottom Schottky
barrier heights of the MIM structures in LRS and HRS as shown in Figure 5.5 (c), it is
clear that the Schottky barrier height at top interface is greatly increased when the MIM
structures are set to LRS as most of the 𝑉𝑂∙ are drifted to the bottom interface, which is in
agreement with the result presented in Chapter 4. In HRS, the Schottky barrier height at
both top and bottom interface (φt-HRS and φb-HRS) decreases with the increasing Ti fluence
because donors including the fixed Ti donors and mobile 𝑉𝑂∙ donors distribute relatively
homogenously over the BFO layer in HRS, and the Schottky barrier height is in inverse
proportion to the doping concentration.[11, 161] As the resulting Ti concentration in the
BFO layer increases with the Ti fluence during Ti implantation into the underlying Pt
bottom electrode, a larger Ti fluence causes a lower Schottky barrier height in HRS.
However, as expected from the negligible Ti concentration close to the top electrode
there is no significant difference between the top Schottky barrier height in LRS (φt-LRS)
for the MIM structures with different Ti fluence which varies between 0.76 eV and 0.99
eV. Most of the mobile 𝑉𝑂∙ are drifted to the bottom interface to lower the bottom
Schottky barrier height in LRS and the donor concentration at the top interface is very
low. Thus, the top Schottky barrier height in LRS is independent of the Ti fluence. The
relationship of the Schottky barrier height in LRS and HRS and the Ti fluence in turn is
a good evidence for the model of modifiable Schottky barrier height for the resistive
switching mechanism discussed in Chapter 4.
5.4 Local resistive switching
The local resistive switching characteristics of the deposited BFO without Au top
electrode were investigated by conductive AFM measurements. A 3×3 µm2 large area on
the BFO was switched to HRS and LRS by scanning a grounded conductive tip over the
BFO surface while a constant voltage bias of +10 V and -10 V was applied to the Pt
bottom electrode, respectively. Note that the voltage polarity is opposite to that in I-V
5.4 Local resistive switching
70
measurements as indicated by the schematic sketch shown in Figure 5.1. After that the
current maps were measured by scanning the conductive tip over the same 3×3 µm2 large
area with a small constant reading voltage of -4 V applied to the Pt bottom electrode as
shown in Figure 5.6. In HRS, only some small leakage current was detected which
homogeneously distributes over the local area. Furthermore, there is no significant
difference for the MIM structures with different Ti fluences. The maximum absolute
value of the current in HRS is 5.79 nA, 5.64 nA and 5.50 nA with increasing Ti fluences.
However, 2-4 conductive spots were observed in LRS. We expect that due to the
nonuniform Ti distribution in BFO grains and BFO grain boundaries during the BFO
deposition at 650 oC and due to the nonuniform voltage drop over the polycrystalline
BFO between conductive AFM tip and large scale bottom electrode, the Schottky barrier
height at bottom BFO/Pt/Ti interface is laterally inhomogeneous after scanning the
conductive AFM tip with writing bias. The current preferentially flows through the
potential barrier minima and conductive spots can be observed.[175] Possibly, the highly
resistive areas can be switched with a writing bias with larger magnitude or longer pulse
length as discussed in Chapter 4.3. The maximum absolute value of the current in LRS
increases with the increasing Ti fluences, i.e., 6.41 nA, 9.96 nA, and 12.81 nA for the
MIM structures with Ti fluence of 5×1015 cm-2, 1×1016 cm-2, and 5×1016 cm-2,
respectively. This is in agreement with the I-V characteristics and the calculated Schottky
barrier heights. The local resistive switching suggests the possibility to scale down the
Figure 5.6: 3D conductive AFM current maps acquired with a reading bias of −4 V
applied on the Pt bottom electrode for the MIM structures with different Ti
fluences in HRS (upper) and LRS (lower).
-3 pA
-8 pAHRS
LRS
Ti fluence 5×1015 cm-2 1×1016 cm-2 5×1016 cm-2
5 Engineering resistive switching by Ti implantation of bottom electrodes
71
nonvolatile resistive switching cell volume which is a function of the Ti distribution in
the BFO thin films and of the film thickness dependent voltage drop.
5.5 Conclusions
In this chapter, we have demonstrated the influence of Ti-implantation of Pt/Sapphire
substrates on the resistive switching characteristics of the subsequently deposited BFO
thin films. The BFO thin films on Ti-implanted Pt/Sapphire substrates show similar
electroforming free bipolar resistive switching characteristics with BFO thin films
fabricated on Pt/Ti/Sapphire and Pt/Ti/SiO2/Si substrates as presented in Chapter 4,
which can be explained by the model of tunable bottom Schottky barrier height in the
MIM structures. In addition to the mobile 𝑉𝑂∙ donors in BFO, the fixed Ti donors diffusing
from the bottom electrodes are also crucial for the electroforming-free bipolar resistive
switching in the BFO-based MIM structures. The Ti diffusion can be engineered by Ti
implantation of the Pt bottom electrodes before the BFO thin film deposition, which
further influences the resistive switching of BFO thin films switches. The diffused Ti
effectively traps and releases oxygen vacancies and consequently stabilizes the resistive
switching in BFO thin film switches. With decreasing Ti fluence the bottom Schottky
barrier height increases, and a larger writing bias is required to fully set/reset the MIM
structures to LRS/HRS. The retention performance can be improved while the endurance
slightly degrades with increasing Ti fluence. This work provides a deeper understanding
of the resistive switching in BFO-based MIM structures with a focus on the role of the
diffused Ti. The ion implantation as a microelectronic compatible process can be scaled
down for generating the local resistive switching via defining a Ti pattern, which will
allow to control the nonvolatile resistive switching cell volume in a CMOS/memristor
hybrid chip.
73
Chapter 6 Resistive switching in BiFeO3/Ti:BiFeO3
thin films with two tunable barriers
As discussed in Chapter 2.3, in addition to being used in the next generation nonvolatile
memories, the resistive switching devices are also a promising candidate for the
nonvolatile reconfigurable logics, which allows researchers to implement beyond von-
Neumann computing to develop compact, low-power devices and systems approaching
brain-like intelligence. There have been many reports on the realization of Boolean logic
functions with BRS or CRS.[20, 23, 24, 176-178] Especially, E. Linn et al. reported that
a single BRS or CRS is sufficient to realize and store the 14 of the 16 Boolean logic
functions (except XOR and XNOR) with a sequential logic approach, which stimulated
strong research interest in the nonvolatile reconfigurable logic applications of resistive
switching devices.
As presented in Chapter 4 and 5, the MIM structures with a BFO single layer showing
the typical bipolar resistive switching is applicable to the sequential logic approach
proposed by E. Linn et al., in which the tunable Schottky barrier only exists in the bottom
interface and the current hysteresis is only observed in the positive bias range in the I-V
characteristics. In this Chapter, we propose to form MIM structures with
BiFeO3/Ti:BiFeO3 (BFO/BFTO) bilayer thin films and the Schottky barrier at both top
and bottom interfaces are tunable with an optimized thickness ratio of BFO and BFTO
layers, in which the current hysteresis exists in both positive and negative bias range in
the I-V characteristics. In particular, the resistance state of BFO/BFTO bilayer structures
depends not only on the writing bias, but also on the polarity of reading bias, which is
different from the conventional bipolar resistive switching. With the same writing bias,
the BFO/BFTO bilayer structures show different resistance state for the different polarity
6.1 Device structure and fabrication
74
of reading bias. The resistance states are stable and distinguishable enough for practical
application. For reconfigurable logic circuits, the polarity of reading bias can be used as
an additional logic variable, i.e. by inverting the polarity of the reading bias the resistance
state of the bilayer structure is inverted under the same writing bias, which makes it
feasible to program and store all 16 Boolean logic functions simultaneously with a same
single cell of a BFTO/BFO bilayer structure in three logic cycles, promising a most
efficient and effective means for implementing beyond von-Neumann computing.
6.1 Device structure and fabrication
To obtain the BFO/BFTO bilayer structures, a BFTO film with nominal 1at% Ti was first
deposited on Pt/Sapphire substrate, and then an undoped BFO film was deposited on the
BFTO film without breaking vacuum and substrate heating by PLD process. Ca. 5 min
has been used to rotate the BFO target to the sputter position and to stabilize the system.
The BFTO and BFO thin films were prepared with the same laser energy, laser repetition
rate, oxygen ambient pressure, and growth temperature, which are 2.6 J/cm2, 10 Hz,
0.013 mbar, and 650 °C, respectively. After the BFO/BFTO deposition, the BFO/BFTO
thin films were in situ annealed at 390 °C with a nominal oxygen ambient pressure of
Substrate
BFTOPt
BFO
Au
Keithley
SourcemeterT1
T2
(b) (a)
Figure 6.1: (a) Schematic sketch of the Au-BFO/BFTO-Pt MIM capacitor structure and
the electric measurement configuration. (b) Cross-sectional bright-field TEM
image of the as-prepared BFO/BFTO bilayer structure consisting of a
nominal 100 nm thick BFTO layer on a 100 nm thick Pt layer on c-sapphire
and a subsequently deposited BFO top layer with a nominal thickness of 500
nm.
6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable barriers
75
200 mbar for 60 min. The nominal thicknesses of BFTO layer are 50 nm, 100 nm, and
150 nm, and the corresponding samples are labelled as sample-50, sample-100 and
sample-150, respectively. The thickness of BFO layer was kept at 500 nm. Following
PLD process, circular Au top contacts with an area of 0.045 mm2 and a thickness of ~100
nm were fabricated by DC magnetron sputtering at room temperature using metal shadow
mask. Thus, a Au-BFO/BFTO-Pt MIM capacitor structure was formed as shown in
Figure 6.1 (a). A schematic sketch of the electric measurement configuration is also
shown in Figure 6.1 (a), which indicates that the electric measurements are carried out
by a Keithley sourcemeter device and the bias voltage is applied between the Au top
electrode (terminal T1) and the Pt bottom electrode (terminal T2). The Pt bottom
electrode is grounded.
Figure 6.1 (b) shows a typical cross-sectional bright-field TEM image of sample-100.
There is no visible interface between BFO and BFTO at a distance of ca. 100 nm from
the Pt bottom contact, which is likely due to the same lattice structure and similar lattice
parameters for BFTO and BFO, and the potential diffusion of Ti which might occur to
the surface of the BFTO layer in the negative temperature gradient during its
preparation.[172] Applying energy-dispersive X-ray spectroscopy with a conventional
Si(Li) detector in scanning TEM mode, Ti could be detected by area analysis neither
above the Pt layer in the ca. 100 nm thick BFTO region nor in the ca. 600 nm thick
BFTO/BFO range (not shown). This may be due to the low Ti content of nominal 1 at. %
in BFTO and to the substitutional incorporation of Ti into the BFTO lattice without Ti
cluster formation.[179] There are some grain boundaries passing through the entire
BFO/BFTO bilayer structure. These grain boundaries may trap oxygen vacancies and
form conductive channels inside the BFO/BFTO film, which may provide a path for
leakage current between BFTO and BFO layer.[11, 180] Therefore, it is supposed that
there is no electron barrier forming at the interface between BFTO and BFO layers.
6.2 Resistive switching characteristics
76
6.2 Resistive switching characteristics
6.2.1 I-V characteristics
Figure 6.2 (a) shows a sequence of ramping voltages for the I-V measurements, namely
two positive triangular voltage sweeps followed by two negative triangular voltage
sweeps. The voltage step is 0.4 V with the step time of 0.1 s. Figure 6.2 (b), (c) and (d)
shows the I-V characteristics of sample-50, sample-100, and sample-150, respectively.
The numbers 1-16 label successive ramping voltages and the corresponding current
branches in the I-V curves, and the arrows indicate the scanning direction of the applied
ramping voltages. Sample-50 and sample-150 show typical bipolar resistive switching
behaviour without an electroforming process, in which the obvious hysteretic I-V
behaviour exists only for negative or positive ramping bias, respectively. However, in
sample-100, the obvious hysteretic I-V behaviours exist in both negative and positive
bias, which shows a symmetric bipolar resistive switching. After a positive writing bias
the structure exhibits low resistive state in positive ramping bias (branch 2, 3, 4, 10, 11
and 12 in sample-100 and sample-150) and high resistance state only in the next negative
ramping bias (branch 5 and 13 in sample-100 and sample-150), after a negative writing
bias the structure shows low resistive state in negative ramping bias (branch 6, 7, 8, 14,
15 and 16 in sample-50 and sample-100) and high resistance state only in the next
positive ramping bias (branch 1 and 9 in sample-50 and sample-100), which indicates the
nonvolatility of the resistive switching. These I-V characteristics are quite stable as the
I-V curves can be well reproduced after 1 month. The low resistance state and high
resistance state in positive ramping bias are abbreviated as PLRS and PHRS,
respectively,[181] which are set and reset by positive writing bias and negative writing
bias and read out by a positive reading bias. The low resistance state and high resistance
state in negative ramping bias are abbreviated as NLRS and NHRS, respectively,[181]
which are set and reset by negative writing bias and positive writing bias and read out by
a negative reading bias. The I-V curve of sample-100 suggests that both positive and
negative reading bias can be used, and different resistance states can be obtained by
6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable barriers
77
different polarities of reading bias with the same writing bias.
6.2.2 Retention and endurance tests
The conventional bipolar resistive switching observed in sample-50 and sample-150 has
been discussed in Chapters 4 and 5. To check the nonvolatility of the states PLRS, NHRS,
PHRS, and NLRS of the new symmetric bipolar resistive switching in sample-100,
retention tests were carried out by first applying a writing bias (+8 V or -8 V) and then
repeating the reading bias (+2 V or -2 V) every 100 seconds at room temperature. As
revealed in Figure 6.3 (a), all PLRS, PHRS, NLRS, and NHRS show increasing
resistance since the detected current decreases. It may be caused by the redistribution of
some charged oxygen vacancies after the writing bias which contribute to the resistive
switching mechanism which will be discussed later. However, PLRS and NLRS become
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
|Curr
ent| (
A)
Voltage (V)
6, 8, 14, 167, 15
5, 13
2, 4, 1
0, 12
3, 11
NLRS
NHRS
1, 9
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
6, 8, 14, 16
7, 15
5, 13
2, 4, 1
0, 12
3, 1
1
PLRS
|Cu
rre
nt| (
A)
Voltage (V)
PHRS
NLRS
NHRS
1, 9
-8 -4 0 4 81E-10
1E-8
1E-6
1E-4
|Curr
ent| (
A)
Voltage (V)
6, 8, 14, 16
7, 15
5, 13
2, 4, 1
0, 12
3, 1
1
PLRS
PHRS
1, 9
(d) (c)
(b) (a)
Figure 6.2: (a) Sequence of ramping voltages. The numbers 1–16 label successive
ramping voltages and the corresponding current branches on a logarithmic
scale of (b) sample-50, (c) sample-100, and (d) sample-150.
6.2 Resistive switching characteristics
78
stable after 5×103 s and 1×104 s, respectively. The low resistance state and high resistance
state are still well defined after 1.8×104 s. The endurance properties with the positive and
negative reading bias were also examined in sample-100 by repeating set/read/reset/read
process for more than 2×104 cycles as shown in Figure 6.3 (b). The set/reset bias is +8 V
or -8 V, and the reading bias is +2 V or -2 V. The PLRS, PHRS, NLRS and NHRS in
endurance tests show the same starting current values as for the retention tests and
gradually increase until saturation due to Joule heating during the endurance tests. After
1×104 cycles, the read currents become stable, and the memory window is well kept after
switching for 2×104 cycles. The low resistance state and high resistance state are
distinguishable and it is expected that the stabilization and reliability of the resistance
states can be further improved by Ar+ irradiation.[41, 174]
6.3 Resistive switching mechanisms
In contrast to the abrupt current change with the formation and rupture of filaments, here
a rather gradually changing current is observed during resistive switching, which
indicates the interface-mediated resistive switching in BFO/BFTO bilayer structures. In
order to get further insight into the interface effect on the resistive switching, the I-V
curves of sample-50, sample-100 and sample-150 in a small voltage range (from -2 V to
0 5 10 15 201E-11
1E-9
1E-7
1E-5
|Curr
ent| (
A)
PHRSU-
writing: - 8 V, U
+
read: +2 V
U+
writing: +8 V, U
-
read: - 2 V
U+
writing: +8 V, U
+
read: +2 V
U-
writing: - 8 V, U
-
read: - 2 V
Time (x103 s)
PLRS
NLRS
NHRS
0 5000 10000 15000 200001E-11
1E-9
1E-7
1E-5
U-
writing: - 8 V, U
-
read: - 2 V
U-
writing: - 8 V, U
+
read: +2 V
NHRS
PHRS
NLRS
|Curr
ent| (
A)
Cycles
PLRS
U+
writing: +8 V, U
-
read: - 2 V
U+
writing: +8 V, U
+
read: +2 V
(b) (a)
Figure 6.3: (a) Retention tests of sample-100 with positive and negative reading bias. The
writing and reading bias for the four independent measurements are indicated
in the legend. (b) Endurance tests of sample-100 with the reading bias of +2
V (black curve) and −2 V (red curve).
6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable barriers
79
+2 V) were measured in two different states, namely after applying a bias pulse of +8 V
and after applying a bias pulse of -8 V for 0.1 s, which are shown in left side of Figure
6.4 (a), (b) and (c). The equivalent circuits corresponding to the bandstructure at different
states are also presented in the right side of Figure 6.4 (a), (b) and (c). As shown in Figure
6.4 (a), the current of sample-50 is small in the both positive and negative voltage range
after applying a positive bias pulse of +8 V, which indicates a head-to-head diode
behavior, while a reverse rectification characteristic is observed after applying a bias
pulse of -8 V, which indicates a reverse diode behavior. This is opposite to the resistive
switching discussed in Chpater 4 and 5. The equivalent circuit of sample-50 after
applying a bias pulse of +8 V is a head-to-head rectifier which consists of two antiserially
connected diodes (Dt and Db) due to the Schottky-like contact (Φt and Φb) formed at both
top (t) and bottom (b) interface and one resistor Ri denoting the bulk resistance of the
BFO/BFTO bilayer structure. The current is always blocked by one of the two Schottky-
like contacts regardless of the voltage polarity. After applying a pulse of -8 V, the
Schottky-like barrier height at the top interface decreases and the diode Dt turns into a
resistor (Rt) whereas the bottom interface remains a Schottky-like contact Db. The current
is controlled by the bottom Schottky-like contact Db and shows a reverse rectification
characteristic. By applying a negative reading bias, Db is forward biased and a large
current flows (NLRS). While a reverse phenomenon is observed in sample-150. As
shown in Figure 6.4 (c), the current is small at both positive and negative voltage range
after applying a bias pulse of -8 V due to the head-to-head rectifier (Dt and Db), and
reveals a forward rectification characteristic after applying a bias pulse of +8 V, which
suggests that the Schottky-like barrier height at bottom interface decreases and the
Schottky-like diode at top interface (Dt) dominates the conductance. By applying a
positive reading bias, Dt is forward and a large current flows (PLRS). However, sample-
100 demonstrates forward and reverse rectification characteristics after applying a bias
pulse of +8 V and -8 V, respectively. This indicates the inversion between a reverse and
a forward rectifier as shown in Figure 6.4 (b). After applying a pulse of +8 V, Schottky-
like contact forms at top interface while Ohmic contact forms at bottom interface. The
current is controlled by the top Schottky-like contact Dt. By applying a positive reading
bias, Dt is forward biased and a large current flows (PLRS); by applying a negative
6.3 Resistive switching mechanism
80
reading bias, Dt is reversed and a small current flows (NHRS). After applying a pulse of
-8 V, Ohmic contact forms at top interface while Schottky-like contact forms at bottom
interface Db. The current is controlled by Db, by applying a positive reading bias, Db is
reversed and a small current flows (PHRS); by applying a negative reading bias, Db is
forward biased and a large current flows (NLRS).
These results suggest that a tunable Schottky-like barrier forms at top interface and
Schottky-like barrier forms at bottom interface in sample-50, Schottky-like barrier forms
at top interface and tunable Schottky-like barrier forms at bottom interface in sample-
150, while the tunable Schottky-like barrier forms at both top and bottom interfaces in
sample-100, and the tunable Schottky-like barrier plays an important role in the resistive
switching of BFO/BFTO bilayer structures. As discussed in Chapter 2.2, the tunable
Schottky-like barrier may come from the migration of charged oxygen vacancies under
the electric field of writing bias[18, 161] and the redistribution of polarization charges
with ferroelectric switching.[37, 43] However, the significant ferroelectric switching was
not observed in the BFO/BFTO bilayer structures within the bias range between -8 V and
+8 V, so the tunable Schottky-like barriers of BFO/BFTO bilayer structures are supposed
to result from the migration of charged oxygen vacancies/ions. Similar to the case of the
MIM structures with a BFO single layer, the BFO/BFTO bilayer structures were also
found to switch faster with larger writing bias (for example, 10 μs at 20 V).This is
consistent with the fact that the drift velocity of oxygen vacancies increases in a larger
electric field,[162, 165] which further confirms that the tunable Schottky-like barrier
comes from the migration of charged oxygen vacancies. The black dots in the right side
of Figure 6.4 indicate the distribution of the movable oxygen vacancies under the certain
writing bias. The accumulation of charged oxygen vacancies in the interface effectively
reduces the corresponding Schottky-like barrier as BFO can be regarded as n-type
semiconductor due to the naturally produced oxygen vacancies,[154, 182] while the
Schottky-like barrier is recovered when the charged oxygen vacancies drift away from
the interface. It is reported that BFO with a small concentration of Ti doping exhibits
higher resistivity than pure BFO.[183, 184] In sample-50, the BFO layer possesses larger
resistance due to the thin BFTO layer, so that most of the applied voltage drops across
the BFO layer. The active region[161] is the top BFO layer which possesses the tunable
6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable barriers
81
Schottky-like barrier at top Au-BFO interface. With the increase of BFTO thickness, the
BFTO layer becomes more resistive and most of the applied voltage drops across the
BFTO layer which results in the active region forming only in bottom BFTO/Pt interface
in sample-150. In sample-100, the resistance of BFO and BFTO is comparable, and both
Figure 6.4: I-V curves from -2 V to +2 V of sample-50 (a), sample-100 (b) and sample-
150 (c) measured after applying a writing bias of +8 V and -8 V. The schematic
band alignment between the top (t) electrode on BFO and the bottom (b)
electrode on BFTO and the corresponding barrier heights (Φt and Φb), the
distribution of the movable oxygen vacancies/ions (the black dots) and
equivalent circuits are also indicated in the right side.
(a)
(b)
(c)
6.3 Resistive switching mechanism
82
BFO and BFTO layers are active regions, so the flexible Schottky-like barrier forms at
both top Au-BFO and bottom BFTO-Pt interfaces.
6.4 Nonvolatile reconfigurable logic applications
6.4.1 Reading bias dependent resistance state
Conventionally, the resistance state of the resistive switching devices only depends on
the external applied writing bias. However, the resistance state of sample-100 depends
not only on the writing bias, but also on the reading bias. Figure 6.5 reveals the
relationship between the resistance states of sample-100 and the polarities of the applied
writing and reading bias. If the writing and reading bias show the same polarity (both are
positive or negative), the bilayer structure exhibits low resistance state (PLRS or NLRS),
otherwise, the bilayer structure shows high resistance state (NHRS or PHRS). The
resistance state of sample-100 is inverted by inverting the polarity of the reading bias
under the same writing bias.
6.4.2 Sequential logic operation
In recent years, a concept of sequential logic [20, 21, 185] has been introduced to realize
the logic functions in a sequential operation with a small set of resistive switching devices.
E. Linn et al.[121] showed that a single BRS or CRS with write-back step can be used to
Figure 6.5: The relationship between the resistance states of sample-100 and the
polarities of the applied writing bias Uwriting and the reading bias Uread.
O
PLRS
NLRS
Uread
U+
read
U-read
UwritingU+
writingU-writing
PHRS
NHRS
6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable barriers
83
realize 14 of 16 Boolean logic functions (except XOR and XNOR) in at most three
sequential logic cycles. Sample-50 and sample-150 with typical bipolar resistive
switching can be used to realize the 14 Boolean logic functions with negative and positive
reading bias respectively. For the first time, we show that all 16 Boolean logic functions
can be realized in three logic cycles with a single BFO/BFTO bilayer structure cell with
symmetric bipolar resistive switching, in which the polarity of the reading bias can be
used as an additional logic variable. Furthermore, all 16 Boolean logic operations can be
started with a same logic cycle, which is very favorable for practical applications. As an
example, in the following we will explain how the Boolean logic function XOR can be
programmed and stored into one BFO/BFTO bilayer structure cell.
Writing bias is determined by the potential of terminal 1 (T1) and terminal 2 (T2) which
depend on the logic variables p and q (1 for high potential and 0 for low potential). Note
that when T1 and T2 are at the same potential (T1=0 and T2=0 OR T1=1 and T2=1), no
potential difference exists across the device, the state of the device is unchanged. As
mentioned above, with the same writing bias the output is different by using different
reading bias. Therefore, the output is defined by T1, T2, initial state of the device (S')
and reading bias (r) which are deemed to be the input variables. For the output, we assign
the low resistance states PLRS and NLRS as logic ‘1’ and the high resistance states PHRS
and NHRS as logic ‘0’. Because the state of the device is either state {PLRS, NHRS} or
state {PHRS, NLRS}, state {PLRS, NHRS} can be assigned to 1 and state {PHRS,
NLRS} can be assigned to 0. Similarly, positive reading bias is assigned to 1 and negative
reading bias is assigned to 0. In Table 6.1, 16 possible combinations for these four input
variables (T1, T2, S' and r) and the corresponding output (Out) are listed, the relationship
between output and input variables can be summarized by this equation:
𝑂𝑢𝑡 = (𝑇1 + 𝑇2 ) ∙ 𝑆′ ∙ 𝑟 + (𝑇1 ∙ 𝑇2) ∙ 𝑆′ ∙ �� + (𝑇1 ∙ 𝑇2 ) ∙ 𝑆 ′ ∙ 𝑟 + (𝑇1 + 𝑇2) ∙ 𝑆′ ∙ �� (6.1)
In general, by initializing the initial state S' to 1 or 0 which can be easily realized by
writing pulse (T1=1, T2=0) or (T1=0, T2=1), respectively, Eq. 6.1 can be reduced to:
𝑂𝑢𝑡 = (𝑇1 + 𝑇2 ) ∙ 𝑟 + (𝑇1 ∙ 𝑇2) ∙ �� (6.2)
or
6.4 Nonvolatile reconfigurable logic applications
84
𝑂𝑢𝑡 = (𝑇1 ∙ 𝑇2 ) ∙ 𝑟 + (𝑇1 + 𝑇2) ∙ �� (6.3)
Based on Eq. 6.2, the Boolean logic function XOR can be implemented by (T1=0, T2=q)
with r=p as shown in Eq. 6.4. XOR is also possible by (T1=1, T2=q) with r=p based on
Eq. 6.3 as shown in Eq. 6.5.
𝑂𝑢𝑡 = 𝑝 𝑋𝑂𝑅 𝑞 = �� ∙ 𝑝 + 𝑞 ∙ �� = (0 + ��) ∙ 𝑝 + (0 ∙ 𝑞) ∙ �� (6.4)
𝑂𝑢𝑡 = 𝑝 𝑋𝑂𝑅 𝑞 = �� ∙ 𝑝 + 𝑞 ∙ �� = (1 ∙ ��) ∙ 𝑝 + (1 + 𝑞) ∙ �� (6.5)
Table 6.1: 16 possible combinations for the four input variables (T1, T2, S' and r) and
the corresponding output (Out). The equations indicate the relationships
between output and the input variables.
T1 T2 S' r Out Equation
0 0 1 1 ‘1’
𝑂𝑢𝑡 = (𝑇1 + 𝑇2 ) ∙ 𝑆′ ∙ 𝑟 1 0 1 1 ‘1’
0 1 1 1 ‘0’
1 1 1 1 ‘1’
0 0 1 0 ‘0’
𝑂𝑢𝑡 = (𝑇1 ∙ 𝑇2) ∙ 𝑆′ ∙ �� 1 0 1 0 ‘0’
0 1 1 0 ‘1’
1 1 1 0 ‘0’
0 0 0 1 ‘0’
𝑂𝑢𝑡 = (𝑇1 ∙ 𝑇2 ) ∙ 𝑆′ ∙ 𝑟 1 0 0 1 ‘1’
0 1 0 1 ‘0’
1 1 0 1 ‘0’
0 0 0 0 ‘1’
𝑂𝑢𝑡 = (𝑇1 + 𝑇2) ∙ 𝑆′ ∙ �� 1 0 0 0 ‘0’
0 1 0 0 ‘1’
1 1 0 0 ‘1’
6.4.3 Reconfigurable Boolean logic operations
Figure 6.6 (a) shows the realization of XOR with three logic cycles C.HV1, C.HV2 and
C.LV (two writing cycles C.HV1 and C.HV2 and one reading cycle C.LV) and the
corresponding experimental demonstrations with the prepared bilayer structure are
shown in Figure 6.6 (b). Contrary to nonvolatile logics, the reading bias in the third logic
cycle C.LV depends on the logic variable p (or q for the other Boolean logic functions).
6 Resistive switching in BiFeO3/Ti:BiFeO3 thin films with two tunable barriers
85
To accommodate nonvolatile logics, a write-back step in the third logic cycle C.LV can
be used to store the output of the logic operations in the same device and make the reading
bias independent of the input logic variables, which is not shown in Figure 6.6. For
example, a positive and negative writing bias is applied in the write-back step to store
the output 1 and 0 of the logic operations into the same device, respectively, and then
both output 1 and 0 can be non-destructively read out by positive reading bias until next
logic operation. Note that the write-back step is only performed in the third logic cycle
C.LV for nonvolatile logics.
The other 15 Boolean logic functions can also be realized with three logic cycles (see the
details in Appendix B). The first logic cycle C.HV1 of all 16 Boolean logic operations
(a)
Figure 6.6: (a) Logic operations for XOR with three logic cycles including two writing
cycles C.HV1 and C.HV2 using ±8 V and one read cycle C.LV using ±2 V
applied to the sample-100. (b) The experimental demonstration of the
sequential XOR for all four input states of p and q. The black and red curves
display the applied potential between T1 and T2 (VT1-VT2) on a linear scale
and the absolute value of the measured current on a logarithmic scale,
respectively. The red dashed line is the current threshold level for Out=‘0’
and Out=‘1’, and the black dotted line is the zero-bias of VT1-VT2.
(b)
6.4 Nonvolatile reconfigurable logic applications
86
can be a positive writing pulse and can be also a negative writing pulse. The nonvolatile
logics can be realized by a write-back step in the third logic cycle C.LV.
6.5 Conclusions
In this chapter, BFO/BFTO bilayer structures with electroforming-free bipolar resistive
switching characteristics have been fabricated by PLD process. With optimized thickness
ratio of BFO and BFTO layers, the current hysteresis exists in both positive and negative
bias range in the I-V curves, which show symmetric bipolar resistive switching
characteristics. The stability and reliability of low resistance states (PLRS and NLRS)
and high resistance states (PHRS and NHRS) in the symmetric bipolar resistive switching
with positive and negative reading bias are examined by retention and endurance tests,
which suggests that the low resistance state and high resistance state are stable and
distinguishable. In the symmetric bipolar resistive switching, the polarity of the reading
bias can be used as an additional logic variable, and the resistance state of symmetric
bipolar resistive switching is inverted by inverting the polarity of the reading bias under
the same writing bias, which makes it feasible to program all 16 Boolean logic functions
into a single cell of a BFO/BFTO bilayer structure in three logic cycles. Nonvolatile logic
is realized by a write-back step in the third logic cycle which stores the output of the logic
operation until next writing cycle in the same cell of a BFO/BFTO bilayer structure.
87
Chapter 7 Summary and outlook
7.1 Summary
The two-terminal passive resistive switching device is one of the most promising
candidates for the next generation memory and nonvolatile logic applications, which can
be used to overcome the von Neumann bottleneck due to the possibility to carry out the
information processing and storage simultaneously and at the same resistive switching
device.
This thesis addresses the key challenges of the resistive switching technology
development, including the underlying physical mechanism of resistive switching in
BFO-based thin films and the engineering of resistive switching by ion implantation. In
addition to the nonvolatile memory, it also exploits the potential of BFO-based resistive
switching devices in the application of reconfigurable nonvolatile logics. The main
conclusions of this thesis are summarized as following.
1. Resistive switching mechanism in BFO-based MIM structures.
Electroforming-free bipolar resistive switching is observed in the Au-BFO-Pt/Ti MIM
structures fabricated by PLD process. The resistive switching behavior is explained by a
model of tunable Schottky barrier formed at BFO-Pt bottom interface. The 𝑉𝑂∙ is mobile
donor in BFO thin films and the distribution of mobile 𝑉𝑂∙ donors can be changed by the
applied writing bias, which changes the Schottky barrier height at BFO-Pt bottom
interface and consequently changes the resistance state of BFO-based MIM structures.
Due to the redistribution of mobile 𝑉𝑂∙ donors after the writing bias, a resistance state
degradation is observed in the retention tests. The endurance can be improved by
introducing a rough BFO-Pt bottom interface thanks to the local electric field
7.1 Summary
88
enhancement around the protrusions and directs the drift of mobile 𝑉𝑂∙ donors under
writing bias pulse. As the mobility of the 𝑉𝑂∙ in BFO thin films exponentially increases
with the electric field, the resistive switching can be continuously configured by tuning
the amplitude and length of the writing bias pulse for the multi-bit memories and logics,
and the switching speed can be increased by slightly increasing the amplitude of the
writing bias.
2. Resistive switching engineering by Ti implantation of bottom electrodes.
In addition to the mobile 𝑉𝑂∙ donors, Ti atoms diffusing from the bottom electrode during
the BFO thin film deposition are also crucial for the resistive switching in BFO-based
MIM structures. Ti acts as fixed donor in BFO thin films which can effectively trap and
release mobile 𝑉𝑂∙ donors and consequently stabilize the resistive switching behavior.
The Ti diffusion can be engineered by Ti implantation of the Pt bottom electrodes before
the BFO thin film deposition, which further influences the resistive switching of BFO-
based MIM structures. With decreasing Ti fluence the bottom Schottky barrier height
increases, and a larger writing bias is required to fully set/reset the MIM structures to
LRS/HRS. The retention performance can be improved with increasing Ti fluence, since
the mobile 𝑉𝑂∙ donors can be more effectively trapped.
3. Reconfigurable nonvolatile logic applications.
In the MIM structure with optimized BFO/BFTO thickness ratio, the current hysteresis
exists in both positive and negative bias range in the I-V curves, because both top and
bottom Schottky barriers are tunable. The resistance state depends not only on the writing
bias, but also on the polarity of reading bias. With the same writing bias, the resistance
state can be inverted by inverting the polarity of the reading bias. For the reconfigurable
logic application, the polarity of reading bias can be used as an additional logic variable.
All 16 Boolean logic functions can be realized by three logic steps in a single
BFO/BFTO-based memristive switch, and the output of the logic operation can be stored
in the same cell of the BFO/BFTO-based memristive switch.
7 Summary and outlook
89
7.2 Outlook
This thesis presents a comprehensive study which provides a solid foundation for more
exciting future work in several directions.
It is noted that the high substrate temperature during BFO thin film deposition in this
work do not necessarily compete the benefits of CMOS compatibility. We suggest to
overcome this challenge by heating the sample surface during growth using laser heating
instead of using resistive heating.
In order to prevent the electric breakdown of the devices, a thick BFO layer is used in
this work. In the future work, it is suggested to reduce the BFO thickness by using a
smaller size top electrodes.
A resistive switching model based on the tunable Schottky barrier is proposed in this
work, and a theory of tunable Schottky barrier height is briefly introduced. A simulation
based on the tunable Schottky barrier remains to be done, which is useful to enable many
circuit design. This work is already underway.
The resistive switching behaviours with a Schottky contact at top interface and a tunable
Schottky barrier at the bottom interface and with the tunable Schottky barrier at both top
and bottom interfaces are presented in this work. The other resistive switching behaviours,
e.g. resistive switching with an Ohmic contact and a tunable Schottky barrier, can be
realized by the ion implantation technology. This work is already underway and close to
completion.
The reconfigurable nonvolatile Boolean logics have been demonstrated with a single
device. The next step is to validate the reconfigurable nonvolatile logics directly on a
BFO-based memristor crossbar array, and to exploit the other logic applications, e.g.
memristor-based flip-flop.
91
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Appendix A
Sample overview
Sample ID Substrate Target Thickness
(nm)
Temperature
(°C) Figure
ID 1543 Pt/Ti/Sapphire BFO 600 650 4.1, 4.2, 4.3, 4.4,
4.6, 4.7, 4.8
ID 1542 Pt/Ti/SiO2/Si BFO 600 650 4.2, 4.3, 4.4
ID 1507 Pt/Sapphire BFO 600 650 4.2
ID 1304 Pt/Ti/SiO2/Si BFO 600 550 4.2
ID 1890 Ti-implanted Pt/Sapphire
(Ti fluence: 5×1016 cm-2) BFO 600 650
5.1, 5.2, 5.3, 5.4,
5.5, 5.6
ID 1891 Ti-implanted Pt/Sapphire
(Ti fluence: 1×1016 cm-2) BFO 600 650
5.1, 5.2, 5.3, 5.4,
5.5, 5.6
ID 1892 Ti-implanted Pt/Sapphire
(Ti fluence: 5×1015 cm-2) BFO 600 650
5.1, 5.2, 5.3, 5.4,
5.5, 5.6
ID 1326 Pt/Sapphire BFTO/BFO 50/500 650 6.2, 6.4
ID 1327 Pt/Sapphire BFTO/BFO 100/500 650 6.1, 6.2, 6.3, 6.4,
6.5, 6.6
ID 1328 Pt/Sapphire BFTO/BFO 150/500 650 6.2, 6.4
The PLD conditions for all sample preparation are the same. The substrate is mounted
onto a sample holder with a target-substrate distance of 60 mm, and is heated up to the
Appendix A
108
deposition temperature listed in the table of sample overview with a ramping rate of
20 °C/min. Before deposition, the PLD chamber is evacuated to a background pressure
of ~6E-4 mbar, and then the oxygen is introduced with an oxygen partial pressure of
1.3E-2 mbar. The laser is calibrated to the desired energy of ~2.6 J/cm2 with a laser spot
size of 0.06 cm2. The repetition rate is 10 Hz, and the pulse number is adjusted according
to the desired thin film thickness. After the deposition, oxygen is introduced into the PLD
chamber with a nominal oxygen pressure of 200 mbar. The substrate is cooled down to
390 °C with a cooling rate of 5 °C/min, and a post-annealing process is applied, the
annealing time is 60 min. Finally, the substrate is naturally cooled down to room
temperature.
109
Appendix B
Logic operations for 15 Boolean logic functions (XOR is shown in Figure 6.6)
𝑝⨁𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 0 𝑞 �� 0 1 1 𝑞 ��
0 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
0 1 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 1 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 0 𝑝 �� 0 1 1 𝑝 ��
0 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 0 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
0 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 1 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
Appendix B
110
0
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 0 𝑝 𝑝 0 1 1 𝑝 𝑝
0 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 0 0 {PLRS, NHRS} {PHRS, NLRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} NHRS=‘0’
0 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 1 0 {PLRS, NHRS} {PHRS, NLRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} NHRS=‘0’
𝑝 + ��
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑞 𝑝 1 0 1 𝑝 𝑞 0
0 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 0 0 {PLRS, NHRS} {PHRS, NLRS} HRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
0 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
𝑝 ∙ ��
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑝 𝑞 0 0 1 𝑞 𝑝 1
0 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
0 1 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
Appendix B
111
𝑝 ∙ 𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 𝑞 𝑝 𝑝 0 1 𝑝 𝑞 �� 0 𝑞
0 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 0 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
0 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
𝑝 ∙ 𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑞 𝑝 �� 0 1 𝑝 𝑞 𝑝
0 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 0 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
0 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
𝑝 + 𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑝 𝑞 𝑝 0 1 𝑞 𝑝 ��
0 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=0 {PHRS, NLRS} {PHRS, NLRS} PHRS=0
1 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS =‘1’
0 1 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
Appendix B
112
𝑝 + 𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑝 𝑞 �� 0 1 𝑞 𝑝 𝑝
0 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
0 1 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
𝑝
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑝 1 1 0 1 1 𝑝 0
0 0 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
0 1 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
��
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑝 1 0 0 1 1 𝑝 1
0 0 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
0 1 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
Appendix B
113
𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑞 1 1 0 1 1 𝑞 0
0 0 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 0 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
0 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
��
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑞 1 0 0 1 1 𝑞 1
0 0 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
1 0 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
0 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 1 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
�� + 𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T1 T2 T1 T2 r T1 T2 T1 T2 r
𝑝 𝑞 s 1 0 𝑝 𝑞 1 0 1 𝑞 𝑝 0
0 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
1 0 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
0 1 0 {PLRS, NHRS} {PHRS, NLRS} PHRS=‘0’ {PHRS, NLRS} {PLRS, NHRS} NHRS=‘0’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} PLRS=‘1’ {PHRS, NLRS} {PHRS, NLRS} NLRS=‘1’
Appendix B
114
�� ∙ 𝑞
C.HV1 C.HV2 C.LV C.HV1 C.HV2 C.LV
T2 T1 T2 r T1 T2 T2 T1 T2 r
𝑝 𝑞 s 𝑝 1 0 1 0 𝑞 𝑝 1 𝑞 0
0 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 1 1 {PLRS, NHRS} {PHRS, NLRS} NLRS=‘1’ {PHRS, NLRS} {PLRS, NHRS} PLRS=‘1’
0 0 0 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
1 1 1 {PLRS, NHRS} {PLRS, NHRS} NHRS=‘0’ {PHRS, NLRS} {PHRS, NLRS} PHRS=‘0’
115
Versicherung
Hiermit versichere ich, dass ich die vorliegende Arbeit ohne unzulässige Hilfe Dritter und
ohne Benutzung anderer als der angegebenen Hilfsmittel angefertigt habe. Die aus fremden
Quellen direkt oder indirekt übernommenen Gedanken sind als solche kenntlich gemacht.
Bei der Auswahl und Auswertung des Materials sowie bei der Herstellung des Manuskripts
habe ich Unterstützungsleistungen von folgenden Personen erhalten:
- Prof. Dr. Oliver G. Schmidt
- Prof. Dr. Xin Ou
- PD Dr. Heidemarie Schmidt
Weitere Personen waren an der Abfassung der vorliegenden Arbeit nicht beteiligt. Die Hilfe
eines Promotionsberaters habe ich nicht in Anspruch genommen. Weitere Personen haben
von mir keine geldwerten Leistungen für Arbeiten erhalten, die im Zusammenhang mit dem
Inhalt der vorgelegten Dissertation stehen.
Die Arbeit wurde bisher weder im Inland noch im Ausland in gleicher oder ähnlicher Form
einer anderen Prüfungsbehörde vorgelegt.
Tiangui You
09. June 2016
117
Theses
of the dissertation
“Resistive switching in BiFeO3-based thin films and reconfigurable logic applications”
For attainment of the title “Dr.-Ing.” at Technische Universität Chemnitz,
Faculty for Electrical Engineering and Information Technology,
presented by M.Eng. Tiangui You
Chemnitz, 09. June 2016
1. Resistive switching devices are promising for next generation memories, thanks to their
simple structure, small feature size, fast write/read speed, and low power consumption.
2. In addition to the highly scalable nonvolatile memory applications, resistive switching
devices can be potentially used for the reconfigurable nonvolatile logics, for
neuromorphic computing, and for hardware-based data encryption.
3. BFO is a well-known multiferroic material and has attracted great interest in the last
decade thanks to its fascinating physical properties, e.g., the coexistence of ferroelectric
and antiferromagnetic characteristics with both above room temperature Curie
temperature and Néel temperature, and photovoltaic effect, which offers the potential
to develop radical new concepts for resistive switching devices.
4. For most of the resistive switching devices, a pretreatment process, called
“electroforming”, is necessary in order to activate the resistive switching behavior by
applying a large voltage or current. Electroforming-free bipolar resistive switching is
observed in the BFO-based MIM structures, which were prepared by pulsed laser
deposition.
Theses
118
5. The bipolar resistive switching mechanism is understood by a model of tunable
Schottky barrier formed at the bottom interface of BFO-based MIM structures due to
the mobile and fixed donors in BFO thin films.
6. Oxygen vacancies are mobile donors in BFO thin films, which can be redistributed
under the writing bias pulse to change the bottom Schottky barrier height in BFO-based
MIM structures and consequently change the resistance of the MIM structures.
7. The Ti atoms diffusing from the bottom electrodes during thin film deposition are
important for the resistive switching in BFO-based MIM structures. The Ti atoms act
as the fixed donors in BFO thin films and can effectively trap and release the mobile
oxygen vacancies. Consequently they are essential for stabilizing the resistive
switching in BFO-based MIM structures.
8. The retention of the resistive switching is stable. It is extrapolated that the on/off ratio
larger than 100 can be well maintained for more than 10 years at 85 °C. The endurance
property can be greatly improved by introducing a rough interface between electrodes
and BFO thin film, because the local electric field can be enhanced around the
protrusions and directs the drift of mobile oxygen vacancies under writing bias pulse.
9. The switching speed can be greatly reduced by slightly increasing the amplitude of the
writing pulse, because the mobility of oxygen vacancy in BFO thin films exponentially
increases with the electric field.
10. The resistive switching of BFO-based MIM structures can be continuously configured
by tuning the amplitude and length of the writing bias pulse, which makes it possible
to realize the multilevel resistive switching for multibit memories and logics.
11. The resistive switching of BFO-based MIM structures can be engineered by the Ti
implantation of bottom electrodes. The retention performance can be improved while
the endurance slightly degrades with increasing Ti fluence.
12. The resistive switching cell can be scaled down to the grain size of BFO which can be
controlled by the thin film thickness and thermal budget of the deposition and post
annealing process. Ion implantation as a CMOS compatible technology can be scaled
down for generating the local resistive switching via defining a Ti pattern, which will
Theses
119
allow to control the nonvolatile resistive switching cell volume in a CMOS/memristor
hybrid chip.
13. The MIM structure with optimized BFO/BFTO thickness ratio shows nonvolatile
resistive switching behavior in both positive and negative bias, because the tunable
Schottky barrier forms at both top and bottom interfaces.
14. In the MIM structure with optimized BFO/BFTO thickness ratio, the resistance states
depend not only on the writing bias, but also on the polarity of reading bias. With the
same writing bias, the resistance state is inverted by inverting the polarity of the reading
bias.
15. For the reconfigurable logic application, the polarity of reading bias can be used as an
addition logic variable. All 16 Boolean logic functions can be realized by three logic
steps in a single BFO/BFTO-based memristive switch, and the output of the logic
operation can be stored in the same cell of the BFO/BFTO-based memristive switch.
121
List of Figures
Figure 2.1 Schematic sketch of a floating-gate MOSFET……….………….…..………5
Figure 2.2 Schematic structure of MRAM cell……………………………...…………..7
Figure 2.3 Schematic device configurations of two types of ferroelectric memory……..8
Figure 2.4 Schematic structure of phase-change memory………………………….......10
Figure 2.5 Schematic structure of RS memory cell…………………………….......…..11
Figure 2.6 I-V characteristics of unipolar and bipolar resistive switching......................12
Figure 2.7 I-V characteristics and schematic views of the filament…...……..…..….…13
Figure 2.8 I-V characteristics, infrared thermal and XRF map images……….…….….15
Figure 2.9 SEM images showing the morphological change by electroforming……..…16
Figure 2.10 Accumulation and removing oxygen vacancies at the top interface…….…17
Figure 2.11 Schematic diagram of Pt/Nb:STO Schottky junction……………….…….18
Figure 2.12 Schematic band diagrams illustrating the variations Schottky barriers……19
Figure 2.13 Illustration of the material implication logic (IMP) operation………….…25
Figure 2.14 Schematic illustration of synapses between neurons. I-V characteristic and
STDP of Ag/Si resistive switching device…………..………………...…..26
Figure 3.1 Schematic of a PLD system………………………………………..…...…..30
Figure 3.2 Schematic sketch of the fabricated MIM capacitor structure and the electric
measurement configuration……………………….…………………..…...32
Figure 3.3 Schematic representation of the DC triangular voltage sweep………..…….33
Figure 3.4 Schematic of the voltage pulses for the retention and endurance tests………34
List of Figures
122
Figure 3.5 Schematic representation of GIXRD setup……………………………….…….35
Figure 4.1 Schematic sketch and typical GIXRD pattern of the as-prepared samples…..40
Figure 4.2 I-V characteristics measured at two pristine cells of the BFO thin films…...41
Figure 4.3 Retention and endurance test results of the BFO-based MIM structures……43
Figure 4.4 Cross-section HAADF-STEM image and EDX mapping images……….…44
Figure 4.5 Schematic presentation of the distribution of mobile and fixed donors …....47
Figure 4.6 I−V curves measured after applying different writing bias…………....……49
Figure 4.7 Temperature dependent I-V characteristics, Schottky-Simmons plot,
temperature-dependent Schottky barrier height and ideality factor…………51
Figure 4.8 AFM topography image, local I-V characteristics measured and current
images measured from LRS and HRS……………………………………………..…...54
Figure 5.1 Schematic of fabrication process and the measurement setups……………..58
Figure 5.2 SRIM calculation, Tof-SIMS profiles, and 3D AFM topography images…...59
Figure 5.3 I-V characteristics with different voltage sweeping sequences.……..…..…62
Figure 5.4 Retention and endurance tests with different Ti fluences………………..…64
Figure 5.5 Bias dependent Schottky barrier heights in HRS, temperature dependent zero-
bias Schottky barrier heights and ideality factors in LRS.………………..…66
Figure 5.6 3D conductive AFM current maps with different Ti fluences…………..….70
Figure 6.1 Schematic sketch of the Au-BFO/BFTO-Pt MIM capacitor structure and the
measurement configuration. Cross-sectional bright-field TEM image……...74
Figure 6.2 Sequence of ramping voltages and the corresponding current………..…….77
Figure 6.3 Retention and endurance tests of sample-100.………………….…………..78
Figure 6.4 I-V curves measured after applying a writing bias of +8 V and -8 V. The
schematic band alignment and the corresponding barrier heights……….….81
List of Figures
123
Figure 6.5 The relationship between the resistance states and the polarities of the applied
writing bias and the reading bias……………….…………….…………..….82
Figure 6.6 Logic operations for XOR and the experimental demonstration…..………..85
125
List of Tables
Table 2.1 Comparison of different memory technologies……………………………...23
Table 4.1 Calculated and fitted coefficients for HRS in Au-BFO-Pt/Ti/Sapphire……..52
Table 5.1 Calculated and fitted coefficients with different Ti fluence……………….…68
Table 6.1 possible combinations for four input variables and corresponding output…..84
127
Acknowledgments
First of all, I express my gratitude to my supervisor Prof. Dr. Oliver G. Schmidt for giving
me this opportunity to pursue my Ph.D. in the Professorship of Material Systems for
Nanoelectronics at Technische Universität Chemnitz. And I would like to thank Prof. Dr.
Xin Ou (Shanghai Institute of Microsystem and Information Technology, Chinese Academy
of Sciences) for being a referee of my doctoral thesis and for many successful collaborations
and fruitful discussions during my work.
I would like to give my sincere gratitude to my advisor PD Dr. Heidemarie Schmidt for
introducing me this interesting topic and for her constant supports on my work. It has been a
great pleasure and honor for me to work in her “Nano-Spintronics” group in the last four
years. I benefited a lot from the discussions we had.
I would like to thank Prof. Dr. Thomas Mikolajick from NaMLab for the valuable
suggestions and fruitful discussions on my research work. I would like to appreciate Dr.
Stefan Slesazeck, Dr. Yao Shuai, Dr. Wenbo Luo, Dr. Huizhong Zeng, Dr. Gang Niu, Florian
Bärwolf, Prof. Dr. Thomas Schröder, Qi Jia, Dr. Wenjie Yu, Prof. Dr. Xi Wang, Dr.
Slawomir Prucnal, Dr. Alexander Lawerenz, Dr. René Hübner, Dr. Stephan Henker, Prof.
Dr. Christian Mayr, Prof. Dr. René Schüffny, Dr. Hartmut Stocker, Dr. Barbara Abendroth,
Dr. Andreas Beyer, and Prof. Dr. Kerstin Volz for the successful collaborations of paper
publications.
I also thank my colleagues from TU Chemnitz, IFW Dresden and HZDR for their kind help
and supports in the last four years. They are Dipl.-Ing. Ilona Skorupa, Dr. Danilo Bürger, Dr.
Rajkumar Patra, Dr. Kefeng Li, Nan Du, Agnieszka Bogusz, Laveen Prabhu Selvaraj, Dr.
Guodong Li, Dr. Feng Zhu, Theresia Göhlert, Sören Lösch, Dr. Shengqiang Zhou, Dr.
Wolfgang Skorupa, PD Dr. Zahn Peter, and Prof. Dr. Sibylle Gemming. Special thanks to
Dipl.-Ing. Ilona Skorupa and Dr. Danilo Bürger for the assistant with PLD system, and
special thanks to PD Dr. Zahn Peter for helping to organize my PLD stays in HZDR.
Acknowledgments
128
I thank all my friends in Germany and in China for their friendship and kindness.
I acknowledge the financial supports from the China Scholarship Council (CSC:
201206970006), and the Initiative and Networking Fund of the Helmholtz Association (VI
MEMRIOX VH-VI-422).
Finally and particularly, I am grateful to my parents, my brother, and rest of my family for
your continuous love, supports and encouragements. Your love will be with me and drive me
continuous progress all my life.
129
Publications and presentations
Peer reviewed journal publications and conference proceedings
1. Tiangui You, Yao Shuai, Wenbo Luo, Nan Du, Danilo Bürger, Ilona Skorupa, René
Hübner, Stephan Henker, Christian Mayr, René Schüffny, Thomas Mikolajick, Oliver G
Schmidt, and Heidemarie Schmidt, Exploiting memristive BiFeO3 bilayer structures for
compact sequential logics, Advanced Functional Materials, 2014, 24, 3357-3365
2. Tiangui You, Nan Du, Stefan Slesazeck, Thomas Mikolajick, Guodong Li, Danilo
Burger, Ilona Skorupa, Hartmut Stocker, Barbara Abendroth, Andreas Beyer, Kerstin
Volz, Oliver G Schmidt, and Heidemarie Schmidt, Bipolar electric-field enhanced
trapping and detrapping of mobile donors in BiFeO3 memristors, ACS Applied
Materials&Interfaces, 2014, 6, 19758-19765
3. Tiangui You, Xin Ou, Gang Niu, Florian Bärwolf, Guodong Li, Nan Du, Danilo Bürger,
Ilona Skorupa, Qi Jia, Wenjie Yu, Xi Wang, Oliver G Schmidt, and Heidemarie Schmidt,
Engineering interface-type resistive switching in BiFeO3 thin film switches by Ti
implantation of bottom electrodes, Scientific Reports, 2015, 5, 18623
4. Tiangui You, Laveen Prabhu Selvaraj, Huizhong Zeng, Wenbo Luo, Nan Du, Danilo
Bürger, Ilona Skorupa, Slawomir Prucnal, Alexander Lawerenz, Thomas Mikolajick,
Oliver G Schmidt, and Heidemarie Schmidt, An energy-efficient, BiFeO3-coated
capacitive Switch with integrated memory and demodulation functions, Advanced
Electronic Materials, 2016, 2, 1500352 (back cover)
5. Agnieszka Bogusz*, Tiangui You*, Daniel Blaschke, Andrea Scholz, Yao Shuai,
Wenbo Luo, Nan Du, Danilo Burger, Ilona Skorupa, Oliver G Schmidt, and Heidemarie
Publications and presentations
130
Schmidt, Resistive switching in thin multiferroic films, 2013 International
Semiconductor Conference Dresden-Grenoble (ISCDG), 2013, 1-4 (*equal contribution)
6. Nan Du, Mahdi Kiani, Christian G Mayr, Tiangui You, Danilo Bürger, Ilona Skorupa,
Oliver G Schmidt, and Heidemarie Schmidt, Single pairing spike-timing dependent
plasticity in BiFeO3 memristors with a time window of 25 ms to 125 μs, Frontiers in
Neuroscience, 2015, 9, 227
7. Lei Jin, Yao Shuai, Xin Ou, Wenbo Luo, Chuanggui Wu, Wanli Zhang, Danilo Bürger,
Ilona Skorupa, Tiangui You, Nan Du, Oliver G. Schmidt, and Heidemarie Schmidt,
Transport properties of Ar+ irradiated resistive switching BiFeO3 thin films, Applied
Surface Science, 2015, 336, 354-358
8. Lei Jin, Yao Shuai, Xin Ou, Pablo F. Siles, Huizhong Zeng, Tiangui You, Nan Du,
Danilo Bürger, Ilona Skorupa, Shengqiang Zhou, Wenbo Luo, Chuanggui Wu, Wanli
Zhang, Thomas Mikolajick, Oliver G. Schmidt, and Heidemarie Schmidt, Resistive
switching in unstructured, polycrystalline BiFeO3 thin films with downscaled electrodes,
Physica Status Solidi A, 2014, 211, 2563-2568
Published patents
1. Tiangui You, Heidemarie Schmidt, Nan Du, Danilo Bürger, Ilona Skorupa, and
Niveditha Manjunath. Complementary resistance switch, contact-connected
polycrystalline piezo-or ferroelectric thin-film layer, method for encrypting a bit
sequence, US Patent: US 2015/0358151 A1 (10.12.2015)
2. Tiangui You, Heidemarie Schmidt, Nan Du, Danilo Bürger, and Ilona Skorupa.
Complementary resistance switch, contact-connected polycrystalline piezo-or
ferroelectric thin-film layer, method for encrypting a bit sequence, US Patent: US
2015/0364682 A1 (17.12.2015)
3. Tiangui You, Heidemarie Schmidt, Nan Du, Danilo Bürger, and Ilona Skorupa.
Komplementärer Widerstandsschalter, dessen Herstellung u.Verwendung, German
Patent: DE102013200615 (17.07.2014)
4. Nan Du, Heidemarie Schmidt, Tiangui You, Danilo Bürger, Ilona Skorupa, and
Publications and presentations
131
Niveditha Manjunath. Komplementärer Widerstandsschalter, Kontaktierte
Polykristalline Piezo- oder Ferroelektrische Dünnschicht, Verfahren zum Verschlüsseln
einer Bitfolge, German Patent: WO2014111481A3, PCT/EP2014/050829 (24.07.2014)
Presentations/Conferences
1. Talk in DPG Spring Meeting 2013, Regensburg, Germany (10.03.2013 - 15.03.2013);
2. Talk in E-MRS Fall Meeting 2013, Warsaw University of Technology, Poland
(16.09.2013 - 20.09.2013)
3. Talk in IEEE 2013 International Semiconductor Conference Dresden - Grenoble
(ISCDG), Dresden, Germany (26.09.2013 - 27.09.2013)
4. Poster in Dresdner Barkhausen-Poster-Preis für Studenten und
Nachwuchswissenschaftler 2013, Dresden, Germany (07.03.2014)
5. 5th Workshop of Novel High k Applications, Dresden, Germany (24.03.2014)
6. Talk in DPG Spring Meeting 2014, Dresden, Germany (30.03.2014 - 04.04.2014)
7. Talk in 6th Forum on New Materials of CIMTEC 2014, Montecatini Terme, Italy
(15.07.2014 - 19.07.2014)
8. Talk in 2nd Meeting Projektbegleitender Ausschuss „Vorlaufforschung an BiFeO3 –
basierter Hardware für die Informationsverarbeitung“, Chemnitz, Germany (22.01.2015)
9. Talk in DPG Spring Meeting 2015, Berlin, Germany (15.03.2015 - 20.03.2015)
10. Poster in Nanoelectronic Days 2015 – “Green IT”, Jülich, Germany (27.04.2015 -
31.04.2015)
11. Talk in 3rd Meeting des SMWK-Verbundprojektes „BFO auf Wafer-Niveau“, Dresden,
Germany (12.06.2015)
12. 73rd Device Research Conference, Columbus, USA (21.06.2015 - 24.06.2015)
13. Talk in 57th Electronic Materials Conference, Columbus, USA (24.06.2015-26.06.2015)
14. Talk in the 16th conference on Defects-Recognition, Imaging and Physics in
Semiconductors, Suzhou, China (2015.09.06-2015.09.10)
133
Curriculum Vitae
Name: Tiangui You
Address: Reichenhainer Str. 39, room 004,
09126 Chemnitz, Germany
Tel: +49 371 531-986133
Email: [email protected]
Education
10/2012 – today Ph.D. student in the Professorship of Material Systems for
Nanoelectronics, Technische Universität Chemnitz, Germany
09/2009 – 06/2012 Master in Physical Electronics, School of Information Science and
Technology, Northwest University, China
09/2005 – 06/2009 Bachelor in Electronic Science and Technology, School of
Information Science and Technology, Northwest University, China
Research experience
10/2012 – today Ph.D. thesis on “Resistive switching in BiFeO3-based thin films and
reconfigurable logic applications” in Technische Universität
Chemnitz, Germany
11/2012 – 10/2015 Guest scientist in the division of Semiconductor Materials (FWIM),
Helmholtz-Zentrum Dresden-Rossendorf, Dresden, Germany
09/2009 – 06/2012 Master thesis on “Preparation and Magnetic, Optical Properties of
ZnO Nanowires by Hydrothermal Process” in Northwest University,
China
12/2007 – 06/2009 Innovation research program on “Preparation and microwave
absorption property of ZnO nano-powder” in Northwest University,
China