------------------------------------------------------------------------------------ Creation Date: 21:12:48 05/06/2010 -- Module Name: RS232/UART Interface - Behavioral-- Used TAB of 4 Spaces----------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uart isgeneric (CLK_FREQ : integer := 50; -- Main frequency (MHz)SER_FREQ : integer := 9600 -- Baud rate (bps));port (-- Controlclk : in std_logic; -- Main clockrst : in std_logic; -- Main reset-- External Interfacerx : in std_logic; -- RS232 received serial datatx : out std_logic; -- RS232 transmitted serial data-- RS232/UART Configurationpar_en : in std_logic; -- Parity bit enable-- uPC Interfacetx_req : in std_logic;-- Request SEND of datatx_end : out std_logic;-- Data SENDEDtx_data : in std_logic_vector(7 downto 0); -- Data to transmitrx_ready : out std_logic;-- Received data ready to uPC readrx_data : out std_logic_vector(7 downto 0) -- Received data );end uart; architecture Behavioral of uart is -- Constantsconstant UART_IDLE : std_logic := '1';constant UART_START : std_logic := '0';constant PARITY_EN : std_logic := '1';constant RST_LVL : std_logic := '1'; -- Typestype state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap -- Signalssignal rx_fsm : state;-- Control of receptionsignal tx_fsm : state;-- Control of transmissionsignal clock_en : std_logic;-- Internal clock enable -- RX Data Tempsignal rx_par_bit : std_logic;signal rx_data_tmp : std_logic_vector(7 downto 0);signal rx_data_cnt : std_logic_vector(2 downto 0); -- TX Data Tempsignal tx_par_bit : std_logic;signal tx_data_tmp : std_logic_vector(7 downto 0);signal tx_data_cnt : std_logic_vector(2 downto 0); begin clock_manager:process(clk)variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);beginif clk'event and clk = '1' then-- Normal Operationif counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 thenclock_en