Elkadig Slide

7/31/2019 Elkadig Slide

1/98

ELE 312

Digital Electronics

DeMassa and Ciccone,Digital Integrated

Circuits, John Wiley & Sons.

Taub and Schilling,Digital Integrated

Electronics, McGraw-Hill

Textbooks


2/98

Contents Basic Properties of Digital Integrated Circuits

Diode Digital Circuits

BJT Digital Circuits Ebers & Moll equations

Transistor modelling

State of transistor in a circuit

Resistor-Transistor Logic (RTL)

Diode-Transistor Logic (DTL)

Transistor-Transistor Logic (TTL)

Schottky Transistor Transistor Logic (STTL)

Different TTL Gates

Emitter-Coupled Logic (ECL)

MOS Digital Circuits NMOS Gates

CMOS Gates

Properties of Digital Integrated

Circuits


3/98

Most important elements: Inverter and Noninverter

Idealized Inverter and Voltage Transfer Characteristics( VTCs)


4/98

Propagation Delays

Rise and fall times and turn-on and turn-off times


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Power dissipation

Logic Element Equivalent Circuit and Fan-out


6/98

Speed-power product = (Average Power Diss) x (Propagation Delay)

Power - Delay Product:

PD = PDISS(avg) x tP(avg)

Diode Digital Circuits


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Diodes

)1(eII TD/VV

SD=

Shockleys Eq

VD V0 = 0.7 V

for Forward Bias


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IV Characteristics

for MN Schottky diodesfor PN Junction diodes

SPICE model

)1(eII TD/VV

SD =


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Basic Logic Gates: AND

Basic Logic Gates: OR


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Clamping Diodes

Level shifting diodes

Level Shifting Diode AND Gate

Level Shifting Diode OR Gate


11/98

BJT Transistors

BJT Fabrication Example


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Multi-Emitter Fabrication Examples

NPN BJT


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Ebers-Moll NPN BJT Model

)1e(II TBEV/V

ESBE,D =

)1e(II TBCV/V

CSBC,D =

BC,DRBE,DE

III =

BC,DBE,DFC III =

CEBIII =

CSRESF

II ==S

I

Reciprocity theorem

transport saturation current

Reverse active (RA)ForwardReverse

Saturation (SAT)ForwardForward

Forward active (FA)ReverseForward

Cutoff (OFF)ReverseReverse

ModeBC junctionBE junction

BJT Modes of Operation


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Reduced models of the operation modes

(a) Cutoff (b) Forward active

(c) Saturation (d) Reverse active

F

FF1

=

R

R

R1

=

1

II BFC

=

IV Characteristics


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Modes of Operation

Examples

F = 65IC, IB = ?

Base and emitter voltages = ?


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TTL Circuit Design

Output-High Pull-up Driver

Output-Low Pull-down Driver

Discharge path and Base-Driving circuitry


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Power Dissipation Example

Resistor-Transistor Logic

(RTL)


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INVERTERVoltage Transfer Characteritics

(VTC)

)FA(BEIL VV =

B

CF

)SAT(CECC

)SAT(BEIHR

R

VVVV

+=

NOR

NAND


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RTL Fan-out

RTL fan-out analysis


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RTL fan-out analysis

Maximum fan-out?

=

IN

OUT

I

IN

C

OUTCC

OUTR

VVI

=

B

)SAT(BEOUT

INR

VVI

=

IHOUTVV =

B

CF

)SAT(CECC

)SAT(BEIHR

R

VVVV

+=


21/98

RTL NONINVERTER


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AND

OR


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RTL with Active Pull-up

Fan-out of RTL with Active Pull-up

Determined by the output

high state as QS is cut-off

for low-inputs

Simplified output high state Simplified input high state


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Simplified output-high fan-out configuration

= IHOH

I

IN

CP

OUT)SAT(CECC

EPOUTR

VVVII

=

2/R

VVI

B

)SAT(BEOUT

IN

=

IH(min)OUT VV =

B

CF

)SAT(CECC

)SAT(BEIHR

R

VVVV

+=


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Diode-Transistor Logic

(DTL)

Basic DTL Inverter

Basic DTL NAND Gate


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Diode Modified DTL Inverter

Transistor Modified DTL Inverter


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VTC of Transistor Modified DTL Inverter

VOH = VCC

VOL = VCE,O(SAT) VIH = VBE,O(SAT) + VBE,L(FA)

VIL = VBE,O(FA) + VBE,L(FA)

DTL Fan-out


low state as DI is off for

high-inputs


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Cascaded DTL

=

IL

OL

I

IN

RC)SAT(O,COL III =

C

)SAT(O,CECC

RCR

VVI

= Path 2

)SAT(O,BF)SAT(O,C II =

RDL,EO,B III =

D

)SAT(O,BE

RD R

VI =

B

)SAT(O,BE)ON(L,D)FA(L,BECC

L,ER

VVVVI

1=For maximum fan-outB

)SAT(O,CE)ON(I,DCC

ILR

VVVI

= Path 3

Example: Calculate the DTL fan-out for F = 49 and = 0.85.

Power Dissipation

Example: Calculate the average power dissipation for the

above example?


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Tansistor-Transistor Logic

(TTL)

Basic TTL Inverter

Basic TTL NAND GateBasic DTL Inverter (compare)


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Actual TTL NAND Gate with Totem Pole Output

VTC of an actual TTL Inverter

VOH = VCC VBE,P(FA) VD,L(ON)

VOL = VCE,O(SAT) VIH = VBE,O(SAT) + VBE,S(SAT) VCE,I(SAT)

VIL = VBE,S(FA) VCE,I(SAT))

VIB = VBE,O(FA) + VBE,S(FA) VCE,I(SAT)VOB = VCC IRCRC VBE,P(FA) VD,L(ON)

D

)FA(O,BE

RDRCR

VII ==


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States of diodes and BJTs

EOC: Edge of conduction

TTL Fan-out


low state as QI is cut-off

for high-inputs


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Cascaded TTL

=

IL

OL

I

IN

)SAT(O,BF)SAT(O,COL III ==C

)SAT(O,BE)SAT(S,CECC

S,C

R

VVVI

=

Path 2RD)SAT(S,E)SAT(O,BIII =

D

)SAT(O,BE

RDR

VI =

B

)SAT(O,BE)SAT(S,BE)RA(I,BCCC

I,BR

VVVVI

=

1=For maximum fan-out

S,CS,B)SAT(S,EIII +=

B

)SAT(O,CE)SAT(I,BECC

ILR

VVV

I

=

Path 1

I,BR)RA(I,CS,B I)1(II +==

Example: Calculate the TTL fan-out for F = 25, =0.85 and R = 0.1

Example (Power Dissipation)

Example: Calculate the average power dissipation for theabove example?

PCC(avg) = 10.4 mW

IRB(OL) = 675 A

IRC(OL) = 2.5 mA

IIL= IRB(OH) = 1 mA

IOL= 51.9 mA51

I

IN

IL

OL =

=

Example (TTL Fan-out)


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Open-Collector TTL

Mostly used in data busses where multiple gate outputs

must be ANDed. This can be accomplished by using a single pull-up resistor

with open-collector TTL gates

This type of connection is referred to as wired-AND.

Low Power TTL (LTTL)

Accomplished simply by increasing the resistance values.

However this results in Decreased fan-out

Longer transient-response times


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LTTL Example

Compare the power dissipation of the LTTL and TTL gates.

IRB(OL) = 67.5 A

IRC(OL) = 200 A

IRB(OH) = 100 A PCC(avg) = 919 W

TTL vs LTTL power dissipation ratio = 10.4 / 0.919 = 11.3

High Speed TTL (HTTL)

Accomplished simply by decreasing the resistance values.

However this results in Increased power dissipation


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Schottky Tansistor-Transistor Logic

(STTL)

Schottky Barrier MN diode

Schottky-clamped BJT (Schottky Transistor)


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Multi-Emitter Fabrication Examples

Modes of Operation for SBJT

1. OFF2. FA3. On Hard4. Reverse Schottky


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Example (SBJT)

Example: Draw the VTC graph of the SBJT inverter shown below

STTL NAND Gate


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STTL NAND Gate (VTC)

VOH = VCC VBE,P(FA) VBE,P2(FA)

VOL = VCE,O(HARD) VIH = VBE,O(HARD) + VBE,S(HARD) VCE,I(HARD)

VIL = VBE,O(FA) + VBE,S(FA) VCE,I(HARD)

STTL NAND Gate (Device states)

Device state table


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STTL Fan-out


low state as QI is cut-off

for high-inputs

Cascaded STTL

=

IL

OL

I

IN

)HARD(O,BF)HARD(O,COL III ==C

)HARD(O,BE)HARD(S,CECC

S,CR

VVVI

=

Path 2, 3)HARD(D,C)HARD(S,E)HARD(O,B

III =

CD

)HARD(D,CE)HARD(O,BE

)HARD(D,CR

VVI

=

B

)HARD(O,BE)HARD(S,BE)RS(I,BCCC

SBDR

VVVVI

=

S,CS,B)HARD(S,EIII +=

B

)HARD(O,CE)HARD(I,BECC

ILR

VVVI

=

Path 1

SBD)RS(I,CS,BIII ==


40/98

Example: Calculate the STTL maximum fan-out for F = 49.

Example (Power Dissipation)

Example: Calculate the average power dissipation for the

above example?

PCC(avg) = 20.05 mW

IRB(OL) = 1.11 mA

IRC(OL) = 4.11 mAIIL= IRB(OH) = 1.32 mA

IOL= 197 mA

149I

IN

IL

OL =

=

Example (TTL Fan-out)

IRCD(OL) = 1.20 mA

IR,O(OL) = 4.02 mA

IE,S(OL) = 4.22 mA

IE,P(OL) = 0.182 mA

IE,P(OH) = 1.3 mA

Low Power STTL (LSTTL)

Accomplished by

1. Increasing the resistance value

2. Diode input section

3. Pull-down enhancements


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Low Power STTL (LSTTL)

LSTTL Example

Compare the power dissipation of the LSTTL and STTL gates.

IRB(OL) = 170 A

IRC(OL) = 463 A

IRB(OH) = 210 A PCC(avg) = 2.11 mW

STTL vs LSTTL power dissipation ratio = 20.05 / 2.11 = 9.5


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Advanced Schottky Tansistor-

Transistor Logic

(ASTTL)

Advanced Schottky TransistorLogic

Advanced Low-Power Schottky TTL (ALSTTL)

Fairchild Advanced Schottky TTL (FAST)

Advanced Schottky TTL (ASTTL)


43/98

ALSTTL

ALSTTL VTC

VOH = VCC VBE,P(FA)

VOL = VCE,O(HARD)

VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) VBE,IPA(FA)

VIL = VBE,O(FA) + VEB,IPA(FA)


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ALSTTL VTC

FAST


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FAST VTC

VOH = VCC VBE,P(FA)

VOL = VCE,O(HARD)

VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) VD,IA(ON)

VIL = VBE,O(FA) + VBE,S(FA)+ VBE,SB(FA) VD,IA(ON)

ASTTL


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ASTTL


47/98

Other TTL Gates

Other TTL Gates

AND gates

NOR gates

OR gates

AND-OR-INVERT (AOI) gates

XOR gates

Schmitt Trigger Inverters and NAND gates

Tri-State buffers


48/98

TTL AND gate

TTL AND gate - VTC


49/98

TTL NOR gate


ICC(LL) = 2 mA

ICC(HL) = 4.175 mA

ICC(LH) = 4.175 mA

PCC(avg) = 17.75 mWICC(HH) = 3.85 mA

IRB(IL) = 1 mA IRB(IH) = 675 A IRC(OL) = 2.5 mA

TTL NAND gate

TTL OR gate

TTL AND gate

Example: Noise margins VNMH , VNML?


50/98

Complex Logic TTL Gate Design

1. ANDing of signals

Multi-emitter input BJT sections

2. ORing of signals

Multiple input sections (QI and RB)

Multiple drive splitting BJTs (QS)

3. If non-inverting ORing is desired

Addional logic inversion circuitry

4. Totem-pole output branch

AND-OR-INVERT (AOI) gate


51/98

Example

Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF

Example

Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF


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TTL XOR gate

Hysteresis and Schmitt Trigger Gates


53/98

Hysteresis

Base-Emitter coupled Schmitt Trigger Non-inverting circuit

Hysteresis

CCOHS VV =

)SAT(CEeq

2CS

)SAT(CECC

1CS

)SAT(BECC

OLS VRR

VV

R

VVV +

=

E2CS1CSeq R||R||RR =

)FA(1S,BEeq

2CS

)SAT(CECC

1CS

)SAT(BECC

IUS VRR

VV

R

VVV +

=

VVVV

)FA(2S,BE)SAT(1S,BECC

IDS

+=

1R

R

E

1CS +=


54/98

Example

Find the VOHS, VOLS, VIUS and VIDS points where RCS1 = 4k, RCS2 = 2.5k, and RES = 1k.

VOHS = 5VV

OLS= 2V VIUS = 2.5V

VIDS = 1.66V

Req = 606

ICS1 = 1.05mA

ICS1 = 1.92mA

TTL Schmitt Trigger NAND gate


55/98

Example

Find the VOH, VOL, VIU and VID points where RCS1 = 4k, RCS2 = 2.5k, and RES = 1k.

VOH = 3.6V

VOL = 0.2V

VIUS = 2.5V

VIDS = 1.66V

VIU = 1.8V

VID = 0.96V

TTL Tri-state Buffers


56/98

TTL Tri-state Buffers

Connecting TTL Tri-state buffers to a Bus


57/98


58/98

Emitter-Coupled Logic

(ECL)

Basic ECL Inverter/Non-inverter

(ECL Current Switch)


59/98

Basic ECL Inverter/Non-inverter VTC

VOH = VCC

According to inverting output: VINV

CI

E

EE)ECL(BEIH

CCOL RR

VVVVV

+=

VIL = VBB 0.05 VIH = VBB + 0.05

E

CI

EE)SAT(BE

E

CI)SAT(BCCC

S

R

R1

)VV(R

RVV

V

+

++=

Example

Calculate the critical VTC points for the ECL current switch

VCC = 5V, VEE = 0V, VBB = 2.6V, RCI = RCR = RE = 1k,

VBE(ECL) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V

VOH = 5V

VOL = 3.10V

VIL = 2.55V

VIH = 2.65V

VS = 3.2V

VINV (VIN = VS) = 2.6V


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Basic ECL NOR/OR Gate


61/98

MECL I NOR/OR Gate

)ECL(BECIDNFCI

)ECL(BEEE

OH VRR)1(R

VV

V ++

=

)ECL(BECI

E

EE)ECL(BEIH

OL VRR

VVVV

+=

Example

Find the logical swing, noise margins and noise immunities for the MECL I

circuit above.

F = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V

VOH = 0.76V

VOL = 1.55V

VIL = 1.225V

VIH = 1.125V

VS = 0.29V

VLS = 0.79V

VNMH = 0.365V

VNML = 0.325V

VNIH = 0.53V

VNIL = 0.475V


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MECL I Fanout

=

IH

OH

I

IN

RDN)FA(BN,EOH III =

DN

EEOHRDN

R

VVI +=

BN,BF)FA(BN,E I)1(I +=

CI

)ECL(BN,BEOH

BN,BR

VVI

=

1

II

F

REIH

+

=

E

EEERE

R

VVI

+=

)ECL(BEOHE VVV =

Fan-out Example

Find the maximum fan-out for the MECL I circuit above

F = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V

Assume load gates reduce VOH by 0.03 volts.

VOH = 0.79V IRDN = 2.205 mA

IB,BN = 148 A

IE,BN = 7.4 mA

IOH = 5.2 mA

VE = -1.54 V

IRE = 2.95 mA

IIH = 59 A

87I

IN

IH

OH =

=


63/98


Find the average power dissipated in the MECL I circuit above

IRE(NOH) = 2.64 mA

IRDN(NOH) = 2.22 mA

IEE(NOH) = 6.685 mA

IRDO(NOH) = 1.825 mA

IRE(NOL) = 2.98 mA

IRDN(NOL) = 1.825 mA

IEE(NOL) = 7.035 mA

IRDO(NOL) = 2.22 mA

PEE(avg) = 35.6 mW

Other ECL Gates


64/98

DeMorgans Theorems

NOR and OR using ANDs and NANDs

NOR:

OR:

NAND and AND using ORs and NORs

NAND:

AND:

BABA =+

BABA =+

BABA +=

BABA +=

Example

Implement the following logic using only ECL gates

)DC)(BA( ++

Solution:

)DC()BA()DC)(BA( +++++


65/98

Collector Dotting Wired-AND Gates

Complex Logic Gates with Collector Dotting


66/98

Example

Series Gating Basic ECL NAND/AND Current Switch


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Series Gating NAND/AND Gate

Complex Logic Gates with Series Gating


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Example

ECL XOR/XNOR Gates


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ECL Decoding Tree


70/98

MOS Logic

MOS Logic

NMOS gates

Fabrication

Modes of operation

NMOS Inverters and Analysis

General NMOS Inverter

Resistor Loaded NMOS Inverter

E-MOSFET loaded NMOS Inverter

D-MOSFET loaded NMOS Inverter


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NMOS (n-channel E-MOSFET) Fabrication Examples

CMOS Fabrication Example


72/98

IV Characteristics

NMOS modes of operation

(a) Cutoff mode (b) Linear mode

(c) Saturation mode (d) body-bias effect

on threshold voltage


73/98

General NMOS Inverter

Graphical analysis when load is a resistor


74/98

Load capacitance

Power dissipation

PDD = VDD (IDD(OH) + IDD(OL)) / 2

VDD IDD(OL)/ 2

(a) Static power dissipation

(b) Transient power dissipation

PD = CL V2DD

: frequency at which the gate is switched

PTOTAL = PDD + PD


75/98

Resistor Loaded NMOS

Resistor Loaded NMOS Inverter


76/98

Propagation Delay

Fall time


77/98

E-MOSFET Loaded NMOS

E-MOSFET Loaded NMOS Inverter


78/98

D-MOSFET Loaded NMOS

D-MOSFET Loaded NMOS Inverter


79/98

NMOS Gates

Symbol Shorthands


80/98

NOR Gate

NOR Gates


81/98

NAND Gate

+=

BA

O

OLL

Wk

)Inverter(V)NAND(V OLOL >

OR Gates


82/98

AND Gates

Example


83/98

AOI (AND-OR-INVERT) Gates

Examples


84/98

XOR/XNOR Gates

Hysteresis


85/98

Schmitt Trigger

Transmission Gate


86/98

Transmission Gate Array

CMOS Logic


87/98

CMOS Inverter

CMOS Inverter


88/98

Symmetric CMOS Inverter

Capacitance Effect on Transition - 1


89/98

Capacitance Effect on Transition - 2

Electrostatic Discharge (ESD) Protection


90/98

CMOS Gates

Symbol Shorthands


91/98

CMOS NAND Gate

CMOS NAND Gates


92/98

CMOS NOR Gate

CMOS NOR Gates


93/98

CMOS AND/NAND Gate

CMOS OR/NOR Gate


94/98

CMOS AOI Gates

CMOS AOI Gates


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CMOS AND-OR Gate

CMOS OAI Gates


96/98

CMOS AOI Gates

Example


97/98

Example


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XOR Gate

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