Altera Time

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    Logic

    Elementarray

    PIN

    Altera IO Element

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    PIN

    Tincomb

    Tiod Tiocomb Tod1

    Altera IOE Timing model

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    IOE Delay

    ! In"#t "at$% Tincomb & in"#t "ad and b#''er to 'attrac( interconnect

    delay

    ! O#t"#t "at$ )combinatorial "at$ *it$ 'at o#t"#t

    le*+

    % Tiod & data delay

    % Tiocomb & combinatorial delay

    % Tod1 & lo* rate , o''- .ccio , .ccint ).cc o' IO "ad iame a internal .cc+

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    Aide $y "rogrammable O#t"#t le*

    ! 4le* rate i t$e mea#re o' $o* 'at an o#t"#t canc$ange 5al#e )mea#red in .olt/4ec+

    ! 6ot 7P8A 5endor o''er t$e ca"ability o'

    "rogramming t$e o#t"#t to be eit$er 'at le* or

    lo* le* &&&&& :

    % 7at 4le* rate ca#e more noie "roblem 5ia gro#nd

    bo#nce- e"ecially *$en m#lti"le o#t"#t are *itc$ing

    %I' yo# $a5e room in yo#r timing "ec- $o#ld #e lo*le* rate i' "oible

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    8ND Bo#nce

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    Altera Logic Element

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    Tl#t Tcomb

    Altera Logic Element

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    6inim#m Pin To Pin Delay

    [Input Pin delay] + [Logic Element Delay] + [Output Delay]

    [Tincomb] + [Tlut + Tcomb] + [Tiod + Tiocomb + Tod1]

    $at abo#t Ro#ting Delay Table 2? $a ro#ting delay

    Tdin2data & delay 'rom dedicated in"#t or cloc( to LE data

    Tamecol#mn & delay 'rom LE o#t"#t to IOE in ame col#mn

    Tamero* & delay 'rom LE o#t"#t IOE in ame ro*

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    6inim#m Pin To Pin Delay

    [Input Pin delay] + [Routing] + [Logic Element Delay] + [Routing] +[Output Delay

    [Tincomb] + [Tdin2data] + [Tlut + Tcomb] +

    [Minimum (ame col!"o#$] + [Tiod + Tiocomb + Tod1]

    [ 2%& ] + ['%] + [1%' + )%*] + min(1%'!%$ + [ 1% +)%) + 2%,]

    - 1'% n

    i' ignore ro#ting- t$en C n )t$i i *$at mar(eting *illF#ote+

    Note t$at ame col#mn ro#ting m#c$ 'ater t$an ro* ro#ting

    )$ence dedicated carry c$ain r#n in col#mn ro#ting+

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    6inim#m Regiter to Regiter

    [Input Pin delay] + [Routing] + [Logic element cloc./to/0] + [Routing] +

    [Logic Element Delay] + [Routing] + [Logic Element etup Time]

    Dedicated

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    6inim#m Regiter to Regiter

    [Input Pin delay] + [Routing] + [Logic element cloc./to/0] + [Routing] +

    [Logic Element etup Time]

    Dedicated

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    Dedicated In"#t/

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    4et#" Time 'or Logic Element

    D77

    GDLHTT# orT# Tl#t

    Ty"ically- t$e et#" time "eci'ication 'or an e>ternal

    data in"#t already acco#nt 'or t$e LHT delay ince t$e

    data in"#t $a to "a t$ro#g$ t$e LHT on it *ay to

    t$e D in"#t

    T$e altera "ec i a bit con'#ing & my bet g#e i t$at

    T# incl#de t$e LHT delay T$ere i no do#bt t$at t$e

    Kilin> .irte> T# "ec incl#de t$e LHT delay

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    Latc$ing in IOE or LE

    ! T$e D77 in t$e IOE can be con'ig#red to eit$erlatc$ incoming data or o#tgoing data

    %

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    6inim#m E>ternal 4et#" Time

    Data latc$ed in LE

    Ro#tingt , 31 n 10n

    13n & ? , ; n

    In"#t

    T#e>tD

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    6inim#m E>ternal 4et#" Time

    Data latc$ed in IOE

    Ro#tingt , C? n 2 & ? , n

    D

    Latc$ing in IOE lo*er t$an in

    Logic Element T$ee are all *ore

    cae n#mber in t$e data$eet *$ic$co#ld acco#nt 'or t$iM alo mentioned

    on "age 2 t$at latc$ing in LE

    element *ill ometime gi5e better

    et#" time t$an an IOE 7or ot$er

    7P8A 'amilie t$i i ##ally not t$e

    cae

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    t+ *ill be

    contraint on $o* 'at data

    i e>c$anged bet*een c$i"

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    PLL e''ect

    PLL/DLL *ill ync$roniJe internal cloc( to e>ternal

    cloc( Aim i to $a5e Jero delay bet*een cloc( edge at

    Logic element and e>ternal cloc( edge

    Ro#ting

    GLHT

    Dedicated