06 Aup Ps2 Jtag-uart-student

8/12/2019 06 Aup Ps2 Jtag-uart-student

1/14


2/14

2

I/O interfacing core from scratch for every device, we will use the provided IP cores (ifavailable). This lesson mainly focuses steps ii and iii above. Specifically, we will learnhow to utilize two pre-built IP cores from Altera in our applications.

3.

DE2-70 Media Computer

Before we develop any application in C, we need to develop the hardware system. Thistask is done using Qsys tool as you have seen in the tutorial and lab 2. To save timefrom creating, generating, port mapping, and compiling a system every time we have anew project, we will use a provided system from Altera University Program (AUP).This system is known as the DE2-70 Media Computer which includes most of thestandard I/O devices that can be used to perform different experiments in this class.

3.1. System Overview

The block diagram of the DE2-70 Media Computer is shown in Fig. 1. The main -components include the Altera Nios-II processor , SRAM , SDRAM and on-chipmemory for program and data storage, an audio-in/out port , a video-out port withboth pixel and character buffers, a PS/2 serial port , a 162 character display , parallelports connected to switches and lights, a timer module, and an RS 232 serial port .

Fig. 1. Block diagram of the DE2-70 Media Computer [1].


3/14

3

A screenshot of the DE2-70 Media Computer in Qsys is shown in Fig. 2.

Fig. 2. Screen shot of the DE2-70 Media Computer in Qsys.

Question: Will your C program from assignment 2 (the tutorial) work with this system?

No. You will need to modify the base addresses.

Note that this system has been verified to work correctly. You will not need to generate,port map, or compile the system.

3.4 PS2 Core

Lets first look at the PS2 core in the DE2_70 Media Computer since we have completed2 labs dealing with a PS2 keyboard. The PS2 Core handles the timing of the PS2 SerialData Transmission Protocol. A driver function or an application can communicate with


4/14

4

the device by reading from and writing to its data and control registers. The core comeswith a 256-word First-In-First-Out (FIFO) buffer for storing data received from a PS2device. A block diagram illustrating connections in an embedded system is shown inthe figure below. Note that the processor does not access to the FIFO buffer or the

controller directly.

Data

Control

NIOS-II

Processor

PS2 Core

FIFO

Controller

Registers

PS2 connector

Altera FPGA

Fig. 3. Interfacing a Nios-II processor with a PS2 Core.

Data and Control Registers

Device drivers or user applications communicate with the PS2 Core through two 32-bit

registers as shown in Table 1.

Table 1. PS2 core register map [2].

(1) Reserved. Read values are undefined. Write zero.

The fields in the data register are explained in Table 2. The PS2 Data register is bothreadable and writable. When bit 15, RVALID , is 1, reading from this register providesthe data at the head of the FIFO in the Data field, and the number of entries in the FIFO(including this read) in the RAVAIL field. When RVALID is 1, reading from the PS2


5/14

5

Data register decrements this field by 1. Writing to the PS/2 Data register can be used tosend a command in the Data field to the PS2 device.

Table 2. Data register of the PS/2 core [2].

The fields in the control register are explained in Table 3. The PS2 control register canbe used to enable interrupts from the PS2 port by setting the RE field to the value 1.When RE field is set, the PS2 port generates an interrupt when RAVAIL > 0. While theinterrupt is pending the field RI will be set to 1, and it can be cleared by emptying thePS2 port FIFO. It means that will need to read all data in the FIFO buffer before exitingthe interrupt service routine (clear the interrupt). The CE field in the PS/2 control

register is used to indicate that an error has occurred when sending a command to a PS2device. In this class, we will mainly deal with receiving data from a PS2 device.

Table 3. Control register of the PS/2 core [2].

Question: What register should a user program communicate with when pollingmethod is used?

Data register


6/14

6

Example: Complete the C program below to read valid data from a PS2 device anddisplay the data on the red LEDs of the DE2 Media Computer. Use polling method.

Question: Why do we need to use the ps2 variable in the previous example? In otherwords can we replace the while loop with

while (1) // loop forever{

if ( ((*PS2_KB_ptr & 0xFFFF0000) >> 16) > 0x0)*(LEDR_ptr) = (*PS2_KB_ptr & 0x000000FF);

}*PS2_KB_ptr indicates a read operation

two read operations are performed by the if statement one byte is lost every time the if statement is executed.

PS2 Core Interrupt

PS2 core setup in Qsys:o

Thiscontrol

register is automatically generated when a PS2 core is addedto the system. PS2 core setup in C program:

o Bit 0 (RE bit) in the control register is set to 1 . Nios-II processor setup in C program:

o Set the interrupt enable bit for the PS2 core IRQ level in register 3 (ienable register) of the Nios-II processor to 1.

#define LEDR_BASE_ADR 0x10000000#define PS2_KB_BASE_ADR 0x10000100

//Main function int main( void ){

volatile int *LEDR_ptr = ( int *) LEDR_BASE_ADR; // LEDR ip core volatile int *PS2_KB_ptr = ( int *) PS2_KB_BASE_ADR; // PS2_KB ip core int ps2; // temporary storage

while (1) // loop forever{

ps2 = *(PS2_KB_ptr);if ( ((ps2 & 0xFFFF0000) >> 16) > 0x0) // check RAVAIL field

*(LEDR_ptr) = (ps2 & 0x000000FF); // output data to red leds

}return 0;}


7/14

7

o Set the global interrupt enable bit in register 0 ( status register) of the Nios-II processor to 1.

Setup the interrupt service routine (ISR) in C program:o Include the exception.h fileo

In the interrupt_handler function, check register 4 ( ipending register) andcall the appropriate ISR function.

o Develop an ISR function to deal with an interrupt event and to clear theinterrupt.

Setup the Altera Monitor Program:o Reserve space for the exception and reset functions at the top of the

memory space.

Example: Complete the C program below to read valid data from a PS2 device anddisplay the data on the red LEDs of the DE2 Media Computer. Use interrupt method.

#include "exception.h" #define LEDR_BASE_ADR 0x10000000#define PS2_KB_BASE_ADR 0x10000100//Main function int main( void ){

int *PS2_KB_ptr = ( int *) PS2_KB_BASE_ADR ; // PS2_KB ip core

// PS2 Core Setup for interrupt *(PS2_KB_ptr + 1) = 0x01; // set RE = 1 to enable interrupt

// Enable individual components and global interrupt bit (Nios side)__builtin_wrctl(3, 0x80); //Enable IRQ7 level __builtin_wrctl(0, 1); //Write 1 into status register

while (1) // loop forever{} // do nothing, wait for interrupt return 0;

}// interrupt handler function --> handle all interrupt events void interrupt_handler( void ){

int ipending;ipending = __builtin_rdctl(4); //Read the ipending register

if ((ipending & 0x80) > 0) //If irq7 is high, run ps2_kb_isr() ps2_kb_isr();

return ;}


8/14

8

Question: Why dont we need to use the ps2 variable in the interrupt example?

Because we dont have to check for valid data in the data register only

one read operation is needed.

3.4 JTAG UART Core

A simple and commonly used scheme for transferring data between a processor and anI/O device is known as the Universal Asynchronous Receiver Transmitter (UART). A UARTinterface (circuit) is placed between the processor and the I/O device. It handles data one 8-bit character (ASCII code) at a time.

We will use a JTAG UART core (named JTAG_UART in the DE2 Media Computer) toestablish a connection between a Nios II processor and the host computer connected tothe DE2_70 board. Fig. 2 shows a block diagram of the JTAG UART circuit. On one sidethe JTAG UART connects to the Avalon switch fabric, which interconnects the Nios IIprocessor, the memory chips, and the I/O interfaces. On the other side it connects to thehost computer via the JTAG port using an USB-Blaster cable. The JTAG UART corecontains two registers: Data and Control , which are accessed by the processor asmemory locations. The core also contains two 64-character FIFOs that serve as storage

buffers, one for queuing up the data to be transmitted to the host and the other forqueuing up the data received from the host.

A block diagram illustrating connections in an embedded system is shown in the figurebelow. Note that the processor does not access to the FIFO buffer or the controllerdirectly.

// ps2 keyboard interrupt service routine void ps2_kb_isr( void ){

int *PS2_KB_ptr = ( int *) PS2_KB_BASE_ADR ; // PS2_KB ip core int *LEDR_ptr = ( int *) LEDR_BASE_ADR;

*LEDR_ptr = (*PS2_KB_ptr & 0x000000FF); // output data to red leds

return ;}


9/14

9

Fig. 4. Block diagram for JTAG UART circuit [3].

Data and Control Registers

Device drivers or user applications communicate with the JTAG UART core throughtwo 32-bit registers as shown in the table below.

Table 4. JTAG UART core register map

Reserved space: Read values are undefined. Write zero.

The fields in the data register are explained in Table 5. When bit 15, RVALID , is 1,reading from this register provides the character (ASCII code) at the head of the FIFO inthe Data field, and the number of entries in the FIFO (after this read) in the RAVAIL

Nios-II

processor


10/14

10

field. When RVALID is 1, reading from the PS2 data register decrements this field by 1.Writing to the data register stores the ASCII value in the write FIFO. If the write FIFO isfull, the character is lost.

Table 5. JTAG UART data register bits [3].

The fields in the control register are explained in Table 6. The JTAG UART control register can be used to enable read or write interrupts from the JTAG UART port bysetting the RE ( for Read interrupt ) or WE ( for Write interrupt ) field to the value 1.

Table 6. JTAG UART control register bits [3].

When RE field is set, the JTAG UART port generates an interrupt whenever the readFIFO is nearly full. The nearly full threshold value is specified at system generation timein Qsys and cannot be changed by the C program. The read threshold value (rtv ) is set to 8in the DE2-70 Media Computer as shown in Fig. 5. The read interrupt condition is setwhenever the read FIFO has rtv or fewer empty spaces remaining. The read interruptcondition is also set if there is at least one character in the read FIFO and no morecharacters are expected. While the interrupt is pending the field RI will be set to 1, andit can be cleared by reading characters from the data register.


11/14

11

The JTAG UART port also can assert a write interrupt whenever the write FIFO isnearly empty. The write threshold value (wtv) is specified at system generation time inQsys and cannot be changed by the C program. The wtv is set to 8 in the DE2-70 MediaComputer as shown in Fig. 5. The write interrupt condition is set whenever there arewtv or fewer characters in the write FIFO. If it has no characters remaining to send, theapplication program should disable the write interrupt. While the interrupt is pendingthe field WI will be set to 1, and it is cleared by writing characters to the data register tofill the write FIFO beyond the wtv.

Fig. 5. Write threshold value (wtv) and read threshold value (rtv) setup.

We will mostly deal with the polling method for the JTAG UART port in the DE2-70Media Computer.

Using JTAG UART Core in Altera Monitor Program

The JTAG_UART core can be used to display text messages (i.e. for troubleshooting) inthe terminal window of the Altera Monitor Program . The terminal window can also beused to and to read in ASCII characters from the host computer via the JTAG_UARTcore. To establish this type of communication, you will need to set the Terminaldevice as JTAG_UART under the System Settings tab as shown in Fig. 6. Theoutput from the JTAG UART core will be displayed in the terminal window. While the C


12/14

12

program is running, you will need to click inside the terminal window to read inputcharacters from the JTAG UART core. An example is shown in Fig. 7.

Fig. 6. JTAG UART setup in Altera Monitor Program.

Fig. 7. An example using JTAG UART core in the Altera Monitor Program.


13/14


14/14

14

4. Exercise

Use an interrupt method to interface with a PS2 keyboard via the PS2 core of the DE2-70Media Computer. Convert the make code of the numeric (0 9), -, +, and enter keys to

ASCII codes and display them in the Altera Monitor Program terminal. Other scancodes should be converted ASCII value of E.

5. References:

[1]. Altera, Media Computer System for the Altera DE -70 Board, for Quartus IIv.13.0, May 2013.

[2]. Altera, PS /2 Core for Altera DE-Series Boards, for Quartus II v.13.0 , May 2012.[3]. Altera, Chapter 6: JTAG UART Core, in the Embedded Peripheral IP User Guide,

June 2011.

06 Aup Ps2 Jtag-uart-student

Documents

Transcript of 06 Aup Ps2 Jtag-uart-student